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Intel and Qihoo 360 Internet Portal Datacenter - Big Data Storage Optimization Case Study

The adoption of cloud computing creates many challenges and opportunities in big data management and storage.

Authored by David Mulnix (Intel) Last updated on 07/06/2019 - 10:47
Blog post

Optimizing Big Data processing with Haswell 256-bit Integer SIMD instructions

Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.

Authored by gaston-hillar (Blackbelt) Last updated on 07/06/2019 - 17:00
Video

Making Big Data and Analytics a reality today

Intel® delivers the performance needed to enable new levels of Apache* Spark* analytics on Intel® Xeon® platforms with Facial Recognition using Apache* Spark* and Apache* Hadoop* technologies.

Authored by Gerald M. (Intel) Last updated on 02/22/2019 - 16:10
Article

Intel® Xeon® Processor E7-8800/4800 V3 Product Family Technical Overview

Contents

1.     Executive Summary 2.     Introduction

Authored by Last updated on 07/06/2019 - 16:40
Blog post

The JITter Conundrum - Just in Time for Your Traffic Jam

In interpreted languages, it just takes longer to get stuff done - I earlier gave the example where the Python source code a = b + c would result in a BINARY_ADD byte code which takes 78 machine instructions to do the add, but it's a single native ADD instruction if run in compiled language like C or C++. How can we speed this up? Or as the performance expert would say, how do I decrease...
Authored by David S. (Blackbelt) Last updated on 07/04/2019 - 20:00
Article

Palestra: Como otimizar seu código sem ser um "ninja" em Computação Paralela

Não perca a palestra "Como otimizar seu código sem ser um "ninja" em Computação Paralela" da Intel que será ministrada durante a Semana sobre Programação Massivamente Paralela em Petrópolis, RJ, no Laboratório Nacional de Computação Científica. Data: 02/02/2016 - 11h30 Local: LNCC - Av. Getúlio Vargas, 333 - Quitandinha - Petrópolis/RJ
Authored by Igor F. (Intel) Last updated on 07/06/2019 - 16:40
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Authored by David Mulnix (Intel) Last updated on 07/06/2019 - 16:40
Blog post

Doubling the Performance of OpenStack Swift with No Code Changes

My current gig is mostly about performance. I manage a group of software engineers dedicated to the languages becoming really important to the cloud and the datacenter.

Authored by David S. (Blackbelt) Last updated on 07/06/2019 - 17:10
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Authored by Last updated on 07/06/2019 - 16:40