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Intel® Debugger Fails to Install on Mac Pro* with Quad-Core Intel® Xeon® 5500 Series Processor and Intel® Xeon® 3500 Series Processor

Intel® Debugger failed to install on Mac Pro with Quad-Core Intel Xeon 5500 series processor and Quad-Core Intel Xeon 3500 series processor
Authored by An Le (Intel) Last updated on 03/26/2019 - 15:36
Article

Optimization of Image Processing Algorithms: A Case Study

High quality image and video processing has become an important part in many professional and consumer applications. This article shares insights and methods gained during a shared work by HP* Labs and Intel on optimizing several imaging algorithms.
Authored by Last updated on 03/28/2019 - 11:56
Article

Troubleshooting InfiniBand connection issues using OFED tools

This article describes how to troubleshoot some common InfiniBand issues using the tools provided by the Open Fabrics Enterprise Distribution (OFED).
Authored by Last updated on 03/09/2019 - 13:08
Article

Understanding how Intel® MPI Library is verified by Intel® Cluster Checker

This article describes how Intel® MPI Library is verified by Intel® Cluster Checker.
Authored by Last updated on 06/01/2018 - 09:20
Article

Understanding the InfiniBand Subnet Manager

The InfiniBand subnet manager (OpenSM) assigns Local IDentifiers (LIDs) to each port connected to the InfiniBand fabric, and develops a routing table based off of the assigned LIDs.

Authored by Last updated on 03/09/2019 - 13:08
Article

Intel® Cluster Ready Archive

An archive of earlier Intel Cluster Ready documents and papers.
Authored by Krotz-Vogel, Werner (Intel) Last updated on 10/11/2017 - 11:28
Blog post

Learning Experience of NUMA and Intel's Next Generation Xeon Processor I

As a technical engineer, I took NUMA as a recent focus, and studied relevant public materials and Intel's next generation Xeon processor in my spare time.

Authored by BRUCE C. (Blackbelt) Last updated on 03/21/2019 - 12:40
Article

How to manually target different Intel® Core™ processors, Intel® Xeon® processors and Intel® Xeon Phi™ processors

Manual cpu dispatch may be used to write code that will be executed only on Intel processors such as 2nd generation Intel® Core™ processors (formerly code named “Sandy Bridge”) and 3rd generation Intel® Core™ processors (formerly code named "Ivy Bridge") with support for Intel® Advanced Vector Extensions, or 4th generation Intel® Core™ processors (formerly code named "Haswell"), 5th generation...
Authored by Martyn Corden (Intel) Last updated on 03/21/2019 - 12:40
Article

Intel Composer XE 2013 Documentation Updates for Intel MIC Architecture

Late-breaking updates to the Intel(R) C++ and Fortran Composer XE 2013 documentation specific to the Intel(R) Many Integrated Core (Intel(R) MIC) architecture will be shown here.

Authored by Last updated on 03/21/2019 - 12:08
Article

PAOS - Packed Array Of Structures

by Jim Dempsey

Authored by jimdempseyatthecove (Blackbelt) Last updated on 12/28/2018 - 11:03