Blog post

Hybrid MPI and OpenMP* Model

In the High Performance Computing (HPC) area, parallel computing techniques such as MPI, OpenMP*, one-sided communications, shmem, and Fortran coarray are widely utilized. This blog is part of a series that will introduce the use of these techniques, especially how to use them on the Intel® Xeon Phi™ coprocessor. This first blog discusses the main usage of the hybrid MPI/OpenMP model.
Authored by Nguyen, Loc Q (Intel) Last updated on 07/06/2019 - 17:10
Blog post

Introduction to OpenMP* on YouTube*

Tim Mattson (Intel) has authored an extensive series of excellent videos as in introduction to OpenMP*.

Authored by Mike P. (Intel) Last updated on 07/04/2019 - 19:51
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Mixing MPI and OpenMP*, Hugging Hardware and Dealing With It

This morning, I took a rare break, and attended a tutorial at Supercomputing.  I'm glad I did.

Authored by James R. (Blackbelt) Last updated on 07/06/2019 - 17:00
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Web Resources about Intel® Transactional Synchronization Extensions

Short URL for this page: www.intel.com/software/tsx

Authored by Roman Dementiev (Intel) Last updated on 07/12/2019 - 11:35
Blog post

Modernizing Software with Future-Proof Code Optimizations

by Henry A. Gabb, Sr. Principal Engineer, Intel Software and Services Group

Authored by Henry Gabb (Intel) Last updated on 07/06/2019 - 17:10
Blog post

The Unfairness of Good Syntax

The unfairness of good syntax - bad syntax is a problem; good syntax is not a solution.
Authored by Last updated on 07/04/2019 - 11:17
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Knights Corner: Open source software stack

Knights Corner: Open source software stack

Authored by James R. (Blackbelt) Last updated on 07/06/2019 - 16:40
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A Guide to Optimization Techniques for the Intel® MIC Architecture

A 3-part educational series on Optimization Techniques for the Intel® MIC Architecture is provided by Colfax Research. The series focuses on select topics on optimization of applications for Intel’s multi-core and manycore architectures (Intel® Xeon® processors and Intel® Xeon Phi™ processors).
Authored by Iman S. (Intel) Last updated on 07/06/2019 - 16:40
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BKMs on the use of the SIMD directive

We had an ask from one of the various "Birds of a Feather" meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences.

Authored by Last updated on 07/06/2019 - 17:00
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Applying Intel® Threading Building Blocks Observers for Thread Affinity on Intel® Xeon Phi™ Coprocessors

In spite of the fact that the Intel® Threading Building Blocks (Intel® TBB) library [1] [2] provides high-level task based parallelism intended to hide sof

Authored by Alex (Intel) Last updated on 07/06/2019 - 17:00