THE GORY DETAILS
Let’s continue from where we left off last time. Let’s figure out the why of the equation,
P = C * V^2 * (a * f)
By now, many of you have heard of Intel® Transactional Synchronization Extensions (Intel® TSX).
In my current position, I work to optimize and parallelize codes that deal with genomic data, e.g., DNA, RNA, proteins, etc.
We had an ask from one of the various "Birds of a Feather" meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences.
Unlike a lot of previous recent blogs, this series is about power management in general. At the very end of the series, I’ll write specifically about the Intel® Xeon Phi™ coprocessor.
Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits.
How about the future? Have we reached the pinnacle of power management?
While talking to a very intelligent but non-engineer colleague, I found myself needing to explain the threading and other components of the current and next generation Intel® Xeon Phi™ archit
Before we start, I will use the next two blogs to clear up some terminology. If you are familiar with these concepts, I give you permission to jump to the next section.
OF COURSE, I KNOW WHAT A THREAD IS….DON’T I?
Now that we know what a core is, let’s dive into another source of confusion.