Using the new concurrent priority queue in Intel® Threading Building Blocks

Authored by Terry Wilmarth (Intel)
We have added a new example that illustrates the use of the concurrent priority queue in Intel® Threading Building Blocks (Intel® TBB). Last updated on 06/26/2012 - 13:33

New Rules for Array Sections in Intel® Cilk™ Plus

Authored by Arch D. Robison (Intel)
This blog covers two important changes in the new specification to improve the language extension. One permits compilers to generate more efficient code. The other resolves a fundamental conflict that array sections brought up. Last updated on 01/29/2013 - 07:55

Generic Parallel Algorithms for Intel® TBB - "They're Already in There" Part 2

Authored by Noah Clemons (Intel)
A high-level overview of general algorithms included in Intel® TBB to let you know what's possible: parallel_reduce, parallel_do, parallel_for_each: parallel_invoke, parallel_pipeline, parallel_sort and parallel_scan Last updated on 06/26/2012 - 13:43

Generic Parallel Algorithms for Intel ® TBB - "They're Already in There" Part 1

Authored by Noah Clemons (Intel)
A high-level overview of some generic parallel algorithms included in Intel® TBB to let you know what's possible: parallel_reduce, parallel_do, parallel_for_each Last updated on 06/26/2012 - 13:38

Understanding the Internals of tbb::graph : Balancing Push and Pull

Authored by Michael Voss (Intel)
This article describes the hybrid push-pull protocol used by Intel® Threading Building Blocks graph Feature Last updated on 08/02/2013 - 11:44

Parallel Studio XE 2013 is here

Authored by James Reinders (Intel)

Today we announced Parallel Studio XE 2013 (available immediately) and

Last updated on 09/06/2013 - 18:26

Architecture Pattern: Compute On Demand

Authored by Asaf Shelly

There are so many examples of applications using pre-processing strategy that it is trivial.

Last updated on 02/20/2014 - 15:39

OpenMP 4.0 may offer important solutions for targeting and vectorization

Authored by James Reinders (Intel)

The upcoming OpenMP 4.0 will be discussed at SC12, and there wil

Last updated on 08/06/2013 - 08:12

Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Authored by Roman Dementiev (Intel)

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

Last updated on 01/29/2014 - 06:09

Using HLE and RTM with older compilers with tsx-tools

Authored by Andreas Kleen (Intel)

To use HLE/RTM to improve lock scalability the lock library needs to be enabled.

Last updated on 06/28/2013 - 16:31