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Parallelization Using OpenMP*

 

Compiler Methodology for Intel® MIC Architecture

Authored by admin Last updated on 03/21/2019 - 12:00
Article

OpenMP* Loop Scheduling

Compiler Methodology for Intel® MIC Architecture

Authored by admin Last updated on 03/21/2019 - 12:00
Article

OpenMP Loop Collapse Directive

Compiler Methodology for Intel® MIC Architecture

Authored by admin Last updated on 03/21/2019 - 12:00
Article

OpenMP* Thread Affinity Control

Compiler Methodology for Intel® MIC Architecture

Authored by admin Last updated on 03/21/2019 - 12:00
Article

OpenMP Related Tips

Compiler Methodology for Intel® MIC Architec

Authored by AmandaS (Intel) Last updated on 03/21/2019 - 12:00
Blog post

Hybrid MPI and OpenMP* Model

In the High Performance Computing (HPC) area, parallel computing techniques such as MPI, OpenMP*, one-sided communications, shmem, and Fortran coarray are widely utilized. This blog is part of a series that will introduce the use of these techniques, especially how to use them on the Intel® Xeon Phi™ coprocessor. This first blog discusses the main usage of the hybrid MPI/OpenMP model.
Authored by Nguyen, Loc Q (Intel) Last updated on 07/06/2019 - 17:10
Article

Hybrid applications: Intel MPI Library and OpenMP*

Tips and tricks on how to get the optimal performance settings for your mixed Intel MPI/OpenMP applications.
Authored by Gergana S. (Blackbelt) Last updated on 07/06/2019 - 19:20
Article

OpenMP* 4.0 Combined Offload Constructs Support for the Intel® Xeon Phi™ Coprocessor

The Intel® Parallel Studio XE 2015 Composer Editions for Windows* and Linux* have feature enhancements that provide near full support of the OpenMP* 4.0 API (July 2013) specification.

Authored by Last updated on 06/14/2019 - 14:35
Article

Process and Thread Affinity for Intel® Xeon Phi™ Processors

The Intel® MPI Library and OpenMP* runtime libraries can create affinities between processes or threads, and hardware resources. This affinity keeps an MPI process or OpenMP thread from migrating to a different hardware resource, which can have a dramatic effect on the execution speed of a program.
Authored by Gregg S. (Intel) Last updated on 07/29/2019 - 08:05
Article

Scale-Up Implementation of a Transportation Network Using Ant Colony Optimization (ACO)

In this article an OpenMP* based implementation of the Ant Colony Optimization algorithm was analyzed for bottlenecks with Intel® VTune™ Amplifier XE 2016 together with improvements using hybrid MPI-OpenMP and Intel® Threading Building Blocks were introduced to achieve efficient scaling across a four-socket Intel® Xeon® processor E7-8890 v4 processor-based system.
Authored by Sunny G. (Intel) Last updated on 07/05/2019 - 19:10