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Intel Cluster Ready FAQ: Customer benefits

Q: Why should we select a certified Intel Cluster Ready system and registered Intel Cluster Ready applications?

Authored by Krotz-Vogel, Werner (Intel) Last updated on 07/06/2019 - 11:10
Article

Intel® Xeon® Processor E7 v3 Product Family

Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Blog post

The JITter Conundrum - Just in Time for Your Traffic Jam

In interpreted languages, it just takes longer to get stuff done - I earlier gave the example where the Python source code a = b + c would result in a BINARY_ADD byte code which takes 78 machine instructions to do the add, but it's a single native ADD instruction if run in compiled language like C or C++. How can we speed this up? Or as the performance expert would say, how do I decrease...
Authored by David S. (Blackbelt) Last updated on 07/04/2019 - 20:00
Article

Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

Proof Points for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

Cache Allocation Technology (CAT) provides benefits across a number of usages, as described in the previous article in this series. This article briefly describes one proof point from the data center (prioritizing a web server to improve its performance) and one from communications (protecting a key communications infrastructure virtual machine (VM)).
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

Software Enabling for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

This article provides a snapshot of some of the software-enabling collateral available for the Cache Allocation Technology (CAT) feature.
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

Proof Points: Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family

This article provides a number of Memory Bandwidth Monitoring (MBM) example proof points and discussion fitting with the usage models described in previous articles.
Authored by Nguyen, Khang T (Intel) Last updated on 07/06/2019 - 16:40
Article

How Intel® Media SDK Screen Capture Plug-in Plays with Video-Streaming Cloud Gaming

Introduction
Authored by Last updated on 01/18/2019 - 11:08