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Article

Using Enhanced Intel SpeedStep® features in HPC Clusters

Summary:

Authored by Michael Hebenstreit (Intel) Last updated on 07/06/2019 - 16:30
Article

Distributed Memory Coarray Programs with Process Pinning

This article describes a method to compile and run a distributed memory coarray program using Intel® Parallel Studio XE Cluster Edition for Linux . An example using Linux* is presented.
Authored by Kenneth Craft (Intel) Last updated on 07/08/2019 - 14:58
Article

Parallelization Using Intel® MPI

Get an overview of parallelization using the Intel® MPI Library and links to additional documentation.
Authored by admin Last updated on 03/21/2019 - 12:00
Blog post

Parallel Universe Magazine #12: Advanced Vectorization

This blog contains additional content for the article "Advanced Vectorization" from Parallel Universe #12:

Authored by Last updated on 07/03/2019 - 20:08
Blog post

OpenMP* 4.0 may offer important solutions for targeting and vectorization

The upcoming OpenMP 4.0 will be discussed at SC12, and there wil

Authored by James R. (Blackbelt) Last updated on 05/28/2018 - 18:28
Article

Intel® Trace Collector Filtering

Filtering in the Intel® Trace Collector will apply specified filters to the trace collection process.  This directly reduces the amount of data collected.  The filter rules can be applied either vi

Authored by James T. (Intel) Last updated on 07/06/2019 - 19:14
Article

Using Intel® MPI Library and Intel® Xeon Phi™ Coprocessor Tips

1. Check prerequisites Each host and each Intel® Xeon Phi™ coprocessor should have a unique IP address across a cluster;
Authored by Dmitry S. (Intel) Last updated on 06/14/2019 - 13:39
Article

Choosing the right threading framework

This is the second article in a series of articles about High Performance Computing with the Intel Xeon Phi.

Authored by Last updated on 07/06/2019 - 16:30
Blog post

Power Configuration Part 0: Introduction: Yikes, there is a lot that is not documented

I was hoping to write a brief two part overview of how to configure the various power settings for the Intel® Xeon Phi™ coprocessor.

Authored by Last updated on 07/06/2019 - 17:00
Article

Resource Guide for Intel® Xeon Phi™ Coprocessor Developers

This article makes recommendations for how a developer can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This is one of three articles: For the Administrator, for the Developer, and for the Investigator. Who is a Developer? Someone who will be programming on an Intel Many Integrated Core (Intel MIC) architecture. The assumption is that they are most...
Authored by Last updated on 07/06/2019 - 16:30