97 Matching Results

Harnessing Handbrake*

By: Maxym Dmytrychenko, Tim Duncan

Authored by Maxym Dmytrychenko (Intel) Last updated on 08/28/2015 - 13:57

Intel® Parallel Studio XE 2016 Beta

Thank you for your interest. The Intel® Parallel Studio XE 2016 Beta program is now closed.

Authored by Gergana S. (Intel) Last updated on 08/25/2015 - 15:32

Debug SPI BIOS after Power Up Sequence

Describe how to halt CPU core, after power up sequence including CPU reset deassertion, to read/display SPI BIOS
Authored by Kan Hayashi (Intel) Last updated on 08/14/2015 - 15:12

Intel® Compiler Options for Intel® SSE and Intel® AVX generation (SSE2, SSE3, SSSE3, ATOM_SSSE3, SSE4.1, SSE4.2, ATOM_SSE4.2, AVX, AVX2, AVX-512) and processor-specific optimizations

Explains which Intel® Compiler switches to use to target and optimize for a specific platform, microarchitecture, CPU or processor.
Authored by Martyn Corden (Intel) Last updated on 08/13/2015 - 17:36

The DRNG Library and Manual

An introduction to the DRNG Library. Includes download links for the static binary libraries, source code, and documentation and a guide to getting started.
Authored by John Mechalas (Intel) Last updated on 08/10/2015 - 16:37

App Promo - Dia dos Namorados - #003 - 28/4/2014

Authored by Juliano Alves (Intel) Last updated on 07/30/2015 - 16:20

Intel Cluster Ready FAQ: Customer benefits

Q: Why should we select a certified Intel Cluster Ready system and registered Intel Cluster Ready applications?

Authored by Werner Krotz-vogel (Intel) Last updated on 07/30/2015 - 12:48

Intel Cluster Ready FAQ: Software vendors (ISVs)

Why should we join the Intel Cluster Ready program?

Authored by Werner Krotz-vogel (Intel) Last updated on 07/30/2015 - 12:47
For more complete information about compiler optimizations, see our Optimization Notice.