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The Intel® AVX Realization of Lanczos interpolation in Intel® IPP 2D Resize Transform

A white paper to describe Intel AVX Realization of Lanczos interpolation in Intel IPP 2D Transform functions.
Authored by admin Last updated on 07/31/2019 - 14:30
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Intel® IPP - Threading / OpenMP* FAQ

This page contains common questions and answers on multi-threading in the Intel IPP.
Authored by Last updated on 07/31/2019 - 14:30
Article

Intel® IPP - Using Intel® IPP in Java* applications

More Information about using Intel® IPP in Java* applications
Authored by Last updated on 07/31/2019 - 14:30
Article

Intel® IPP Memory Function ippMalloc/Free FAQ

Information about Intel® Integrated Performance Primitives (Intel® IPP) memory functions
Authored by Last updated on 07/31/2019 - 14:30
Article

Using Intel® IPP Threaded Static Libraries

Q: How to get Intel® Integrated Performance Primitives (Intel® IPP) Static threaded libraries?

Authored by Last updated on 07/31/2019 - 14:30
Article

OpenMP* and the Intel® IPP Library

How to configure OpenMP in the Intel IPP library to maximize multi-threaded performance of the Intel IPP primitives.
Authored by Last updated on 07/31/2019 - 14:30
Article

Intel® IPP Functions Optimized for Intel® Advanced Vector Extensions 2 (Intel® AVX2)

List of Intel IPP functions optimized for processor code name Haswell and Skylake
Authored by Shaojuan Z. (Intel) Last updated on 07/31/2019 - 14:30
Article

Threading Intel® Integrated Performance Primitives Image Resize with Intel® Threading Building Blocks

Threading Intel® IPP Image Resize with Intel® TBB.pdf (157.18 KB) :
Authored by Jeffrey M. (Intel) Last updated on 07/31/2019 - 15:05
Blog post

Celebrating a Decade of Parallel Programming with Intel® Threading Building Blocks (Intel® TBB)

This year marks the tenth anniversary of Intel® Threading Building Blocks (Intel® TBB).

Authored by Sharmila C. (Intel) Last updated on 08/01/2019 - 09:30
Article

Intel® Compiler Options for Intel® SSE and Intel® AVX generation (SSE2, SSE3, SSSE3, ATOM_SSSE3, SSE4.1, SSE4.2, ATOM_SSE4.2, AVX, AVX2, AVX-512) and processor-specific optimizations

  What are the IA-32 and Intel® 64 processor targeting options in the Intel® compilers?
Authored by Martyn Corden (Intel) Last updated on 01/07/2019 - 15:51