Article

Controlling floating-point modes when using Intel® Threading Building Blocks

Intel® Threading Building Blocks (Intel® TBB) 4.2 Update 4 introduced enhanced support for managing floating-pointing settings.

Authored by Alexei K. (Intel) Last updated on 05/27/2016 - 12:12
Article

Floating-point Settings in Worker Threads May Differ from Master Thread for OpenMP, TBB and Intel Cilk Plus

Worker threads created by OpenMP, Intel Cilk Plus or Intel Threading Building Blocks may have different initial floating-point environments compared to the master thread that spawned them. This can lead to slight differences in floating-point results.
Authored by Martyn Corden (Intel) Last updated on 04/07/2016 - 15:58
Article

Run-to-Run Reproducibility of Floating-Point Calculations for Applications on Intel® Xeon Phi™ Coprocessors (and Intel® Xeon® Processors)

The Issue

If I rerun the identical program on the identical input data on an identical processor, will I get an identical result?

Authored by Martyn Corden (Intel) Last updated on 03/31/2016 - 23:18
Article

Multiple definitions of floating-point exception parameters such as FPE_M_TRAP_OVF

Referencing parameters related to floating-point exceptions via the IFLPORT or IFCORE and IFPORT modules may give errors such as error #6405: The same named entity from different modules and/or program units cannot be referenced. [FPE_M_TRAP_DIV0]
Authored by Martyn Corden (Intel) Last updated on 02/14/2016 - 10:19
Article

Consistency of Floating-Point Results using the Intel® Compiler

Why doesn’t my application always give the same answer? Tradeoffs between floating-point accuracy, reproducibility and performance are discussed with examples;recommendations are made for improving reproducibility while limiting the impact on performance. With initial updates for Intel® Parallel Studio XE 2016, Composer Edition, containing the Intel® Compiler version 16.
Authored by Martyn Corden (Intel) Last updated on 02/04/2016 - 13:27
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