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A Future Without Cords: Wireless Charging

Imagine this scenario: you walk into the airport lounge, waiting for a flight that is now delayed by three hours.

Authored by Wendy B. (Intel) Last updated on 06/14/2017 - 15:45
Blog post

Write your first program with Haswell new instructions

It has been almost a year since the Haswell new instructions have been announced b

Authored by Thomas Willhalm (Intel) Last updated on 06/14/2017 - 15:58
Blog post

Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

Authored by Roman Dementiev (Intel) Last updated on 06/14/2017 - 15:53
Blog post

Processing Arrays of Bits with Intel® Advanced Vector Extensions 2 (Intel® AVX2)

It is only a few weeks until you will get a chance to get your hands on the 4th Generation Intel® Core&tm; Processor Family

Authored by Thomas Willhalm (Intel) Last updated on 06/14/2017 - 15:53
Article

Accelerate Performance Using OpenCL* with Intel® HD Graphics

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Authored by Eli Hernandez (Intel) Last updated on 06/07/2017 - 10:42
Blog post

We Are Go for Haswell!

You’ve been waiting for the highly anticipated 4th generation Intel® Core™ processor family, and it’s finally here.

Authored by Wendy B. (Intel) Last updated on 06/14/2017 - 16:02
Blog post

Intel® vPro Technology™ Release 9.0: Platform Requirements

Intel has launched the latest 2-Chip Haswell processors supporting Intel® AMT Release 9.0. This marks the 4th Generation Intel® Core™ i5 and i7 Processors.

Authored by Gael H. (Intel) Last updated on 06/14/2017 - 15:46
Blog post

The Chronicles of Phi - part 1 The Hyper-Thread Phalanx

The term phalanx is derived from a military formation used by the ancient Greeks and Romans. The formation generally involved soldiers lining up shoulder to shoulder, shield to shield multiple rows deep. The formation would advance in unison becoming “an irresistible force.” I use the term Hyper-Thread Phalanx to refer to the Hyper-Thread siblings of a core being aligned shoulder-to-shoulder and...
Authored by jimdempseyatthecove Last updated on 06/14/2017 - 16:03
Blog post

Indexing the Mahabharata

by N. Shamsundar

Authored by mecej4 Last updated on 06/14/2017 - 16:26
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