3 Matching Results

Intel® Xeon Phi™ Coprocessor code named “Knights Landing” - Application Readiness

As part of the application readiness efforts for future Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors (code named Knights Landing), developers are interested in improving two key aspect

Authored by Indraneil Gokhale (Intel) Last updated on 02/10/2015 - 08:02

Analyzing Intel® SDE's TSX-related log data for capacity aborts

Starting with version 7.12.0, Intel® SDE has Intel® TSX-related instruction and memory access logging features which can be useful for debugging Intel® TSX's capacity aborts.

Authored by HASSAN SALEHE MATAR (Intel) Last updated on 01/27/2015 - 08:19

Using Intel® SDE's chip-check feature

Intel® SDE includes a software validation mechanism to restrict executed instructions to a part

Authored by Mark Charney (Intel) Last updated on 10/11/2013 - 09:53
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