14 Matching Results
Article

Performance of Multibuffer AES-CBC on Intel® Xeon® Processors E5 v3

This paper examines the impact of the multibuffer enhancements to OpenSSL* on the Intel® Xeon® processor E5 v3 family when performing AES block encryption in CBC mode.

Authored by John Mechalas (Intel) Last updated on 07/13/2015 - 16:05
Article

Improving OpenSSL Performance

Contents

AbstractOverview of OpenSSL

Authored by admin Last updated on 06/01/2015 - 10:48
Blog post
Article

AES-GCM Encryption Performance on Intel® Xeon® E5 v3 Processors

This case study examines the architectural improvements made to the Intel® Xeon® E5 v3 processor family in order to improve the performance of the Galois/Counter Mode of AES block encryption.

Authored by John Mechalas (Intel) Last updated on 04/01/2015 - 11:54
Blog post
Blog post

Fast SHA-1

Hello. If the speed of widely used cryptography algorithms (like AES or SHA-1) is of some interest to you, dear reader, then I’m welcoming you to this blog.

Authored by Max Locktyukhin (Intel) Last updated on 03/20/2015 - 21:22
Blog post

How Intel® QuickAssist Technology Accelerates Deep Packet Inspections and other Network Function Use Cases

Intel® QuickAssist Technology Introduction
Authored by David Mulnix (Intel) Last updated on 01/29/2015 - 12:00
Blog post

Encryption/Decryption - invoking OpenSSL API through JNI calls

This blog outlines the steps needed to integrate Intel’s AES-NI instructions into an Android app via the OpenSSL library.

Authored by Neelima K. (Intel) Last updated on 12/05/2014 - 16:15
Blog post

New Features in Intel® Active Management Technology (AMT) 10

While Intel did not release an Intel® vProTM Technology desktop with  ME (Intel

Authored by Colleen Culbertson (Intel) Last updated on 09/17/2014 - 12:58
Article

Performance Impact of Intel® Secure Key on OpenSSL

The goal of this paper is to demonstrate the performance gains obtained when using the Intel® Secure Key in applications that depend on OpenSSL* for cryptographically secure random numbers.
Authored by John Mechalas (Intel) Last updated on 01/07/2014 - 14:03
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