34 Matching Results
Video

Pt. 1 of 4 - Optimize your Fortran Application for SIMD and Multi-Core

Moore’s Law no longer gives us steadily increasing clock speeds, but instead gives us more cores and wider SIMD units.

Authored by admin Last updated on 07/28/2015 - 04:04
Video

Pt. 2 of 4 - Optimize your Fortran Application for SIMD and Multi-Core

Moore’s Law no longer gives us steadily increasing clock speeds, but instead gives us more cores and wider SIMD units.

Authored by admin Last updated on 07/28/2015 - 04:04
Video

Pt. 3 of 4 - Optimize your Fortran Application for SIMD and Multi-Core

Moore’s Law no longer gives us steadily increasing clock speeds, but instead gives us more cores and wider SIMD units.

Authored by admin Last updated on 07/28/2015 - 04:04
Video

Pt. 4 of 4 - Optimize your Fortran Application for SIMD and Multi-Core

Moore’s Law no longer gives us steadily increasing clock speeds, but instead gives us more cores and wider SIMD units.

Authored by admin Last updated on 07/28/2015 - 04:04
Article

About Intel Cilk™ Plus and How To Get Started

This article has been updated for Intel C++ Composer XE 2013 and 2013 SP1 for Windows,  Linux* and Mac OS* X.

Authored by Jennifer J. (Intel) Last updated on 07/21/2015 - 17:02
Video

Episode 2.1 - Purpose of the MIC architecture

In this video episode 2.1 we will introduce Intel Xeon Phi coprocessors based on the Intel Many Integrated Core, or MIC, architecture and will cover some of the specifics of hardware implementation

Authored by admin Last updated on 07/01/2015 - 15:50
Article

XML Parsing Accelerator with Intel® Streaming SIMD Extensions 4 (Intel® SSE4)

This white paper will describe how Intel XML parsing can benefit from Intel® Streaming SIMD Extensions 4 (Intel® SSE4), a new set of Single Instruction Multiple Data (SIMD) instructions designed to improve the performance of various applications, such as video encoders, image processing, 3D games, and string/text processing.
Authored by Deleted User Last updated on 05/08/2015 - 12:03
Video

Episode 2.2 - Details of Intel MIC Architecture

In this video we will discuss the general properties of the Intel MIC architecture in detail, and then focus on vector instruction support.

Table of Contents:

Authored by admin Last updated on 05/06/2015 - 19:46
Article

x87 and SSE Floating Point Assists in IA-32: Flush-To-Zero (FTZ) and Denormals-Are-Zero (DAZ)

Introduction
Authored by Last updated on 05/04/2015 - 06:08
Article

Schema Validation with Intel® Streaming SIMD Extensions 4 (Intel® SSE4)

Introduction
Authored by Yongnian Le (Intel) Last updated on 04/22/2015 - 13:28
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