Forum topic

Vectorization - Speed up expected for SSE and AVX

I am doing a benchmark about vectorization on MacOS with the following processor i7 :

$ sysctl -n machdep.cpu.brand_string

    Intel(R) Core(TM) i7-4960HQ CPU @ 2.60GHz

Authored by henry petit Last updated on 04/27/2017 - 10:50

Intel® ISA-L: Cryptographic Hashes for Cloud Storage

Intel Intelligent Storage Acceleration Library (Intel ISA-L) generates cryptographic hashes fast using Intel AES-NI, SSE, AVX, and AVX2. This code sample will get you started coding.
Authored by Thai Le (Intel) Last updated on 04/26/2017 - 16:01

Intel Resources for Game Developers

Intel® HD Graphics and Intel® Iris™ and Iris™ Pro Graphics parts are some of the most commonly used graphics solutions in PCs worldwide. By following the advice on these pages and using the tools we provide, you'll ensure that your game is able to be enjoyed by millions of gamers. We want you to be successful
Authored by Colleen C. (Intel) Last updated on 04/26/2017 - 15:28
Forum topic

Data source for intrinsics guide

I'm working on an open source project to implement portable versions of SIMD intrinsics.  I've been using the

Authored by Evan N. Last updated on 04/24/2017 - 19:28
Forum topic

List of interrupss


I have a C console programs running under Windows 10. I have compiled it with icl. I am looking into writing __asm{ code to serialize theard processing

Authored by Joseph Reichman Last updated on 04/23/2017 - 09:36
Forum topic

Is PTWRITE and POWERSTAT Packets supported on 7th core processor?

I read Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, and there're 2 new packets in Processor Trace. They're not supported on my cpu, i7-6700.

Authored by claw L. Last updated on 04/20/2017 - 08:53
Forum topic

QPI will abort TSX transactions?

On a system with at least two NUMA nodes - will an accessing cache-lines from another NUMA node (through QPI) abort a RTM/HLE transaction?

I can't find a hint in the Intel documentation.

Authored by Oliver K. Last updated on 04/15/2017 - 22:30
Forum topic

Why is Intel allowing this?!?

I am not sure if this is the right forum for this topic, but given that it concerns new CPUs such as Kaby Lake I decided to start it here.

Authored by Igor Levicki Last updated on 04/14/2017 - 17:01

Vectorize or Die part 2 - Examples vectorizing C++ and Fortran

To get the full performance benefit from today’s and tomorrow’s hardware, software must be both threaded and vectorized.

Authored by admin Last updated on 04/13/2017 - 09:07
Forum topic

meaning of RTM abort status

I've read 'Intel 64 and IA-32 Architectures Software/Optimization Manual' but I've some questions regarding to the RTM abort status.

Under which conditions are the bits in EAX set:

Authored by Oliver K. Last updated on 04/13/2017 - 05:13
For more complete information about compiler optimizations, see our Optimization Notice.