Filters

Article

How to manually target different Intel® Core™ processors, Intel® Xeon® processors and Intel® Xeon Phi™ processors

Manual cpu dispatch may be used to write code that will be executed only on Intel processors such as 2nd generation Intel® Core™ processors (formerly code named “Sandy Bridge”) and 3rd generation Intel® Core™ processors (formerly code named "Ivy Bridge") with support for Intel® Advanced Vector Extensions, or 4th generation Intel® Core™ processors (formerly code named "Haswell"), 5th generation...
Authored by Martyn Corden (Intel) Last updated on 03/21/2019 - 12:40
Blog post

Using HLE and RTM with older compilers with tsx-tools

To use HLE/RTM to improve lock scalability the lock library needs to be enabled.

Authored by Andreas Kleen (Intel) Last updated on 06/14/2017 - 13:26
Blog post

TSX fallback paths

The need for fallback paths
Authored by Andreas Kleen (Intel) Last updated on 06/14/2017 - 13:26
Blog post

Transactional memory support: the speculative_spin_mutex

Intel recently released the 4th Generation Intel® Core™ processors, which have Intel® Transaction

Authored by Last updated on 05/28/2018 - 18:30
Blog post

Transactional Memory Support: the speculative_spin_rw_mutex (Community Preview Feature)

In a previous post I discussed the Intel® Tra

Authored by Last updated on 06/14/2017 - 15:46
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

Authored by Andreas Kleen (Intel) Last updated on 06/07/2017 - 10:53
File Wrapper

Parallel Universe Magazine - Issue 17, March 2014

Authored by admin Last updated on 03/21/2019 - 12:00