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Coarse-grained locks and Transactional Synchronization explained

Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this

Authored by James R. Last updated on 06/14/2017 - 16:00
Blog post

Transactional Synchronization in Haswell

Intel has released details of Intel® Transactional Synchronization Extensions (Intel® TSX) for the future multicore processor code-named “Haswell”.

Authored by James R. Last updated on 06/14/2017 - 16:03
Article

How to manually target different Intel® Core™ processors, Intel® Xeon® processors and Intel® Xeon Phi™ processors

Manual cpu dispatch may be used to write code that will be executed only on Intel processors such as 2nd generation Intel® Core™ processors (formerly code named “Sandy Bridge”) and 3rd generation Intel® Core™ processors (formerly code named "Ivy Bridge") with support for Intel® Advanced Vector Extensions, or 4th generation Intel® Core™ processors (formerly code named "Haswell"), 5th generation...
Authored by Martyn Corden (Intel) Last updated on 12/18/2017 - 10:38
Blog post

Intel® Transactional Synchronization Extensions (Intel® TSX) profiling with Linux perf

Intel® TSX exposes a speculative execution mode to the programmer to improve locking performance.. Tuning speculation requires heavily on a PMU profiler.

Authored by Andreas Kleen (Intel) Last updated on 06/14/2017 - 15:38
Blog post

Using HLE and RTM with older compilers with tsx-tools

To use HLE/RTM to improve lock scalability the lock library needs to be enabled.

Authored by Andreas Kleen (Intel) Last updated on 06/14/2017 - 13:26
Blog post

Web Resources about Intel® Transactional Synchronization Extensions

Short URL for this page: www.intel.com/software/tsx

Authored by Roman Dementiev (Intel) Last updated on 06/14/2017 - 16:43
Blog post

TSX fallback paths

The need for fallback paths
Authored by Andreas Kleen (Intel) Last updated on 06/14/2017 - 13:26
Blog post

Transactional Memory Support: the speculative_spin_rw_mutex (Community Preview Feature)

In a previous post I discussed the Intel® Tra

Authored by Christopher Huson (Intel) Last updated on 06/14/2017 - 15:46
Article

TSX anti patterns in lock elision code

Lock elision is a new way to scale programs. It requires following some rules for correctness and good performance.

Authored by Andreas Kleen (Intel) Last updated on 06/07/2017 - 10:53
Video

What’s New in the Intel® VTune™ Amplifier XE 2015 Beta release

Note: Video portion will load in about 1 minute, audio will start immediately

Authored by MrAnderson (Intel) Last updated on 02/12/2018 - 13:49
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