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Case Study: Computing Black-Scholes with Intel® Advanced Vector Extensions

This case study discusses Intel® Advanced Vector Extensions (Intel® AVX) and gives an overview of the Black-Scholes valuation.
Authored by shuo-li (Intel) Last updated on 01/26/2017 - 00:49
Article

Case Study: Achieving High Performance on Monte Carlo European Option Using Stepwise Optimization Framework

Read this case study that discusses the Monte Carlo method of statistical computing to solve complex scientific computing problems.
Authored by shuo-li (Intel) Last updated on 01/26/2017 - 00:49
Article

Black-Scholes-Merton Formula on Intel® Xeon Phi™ Coprocessor

Get access to source code and test workloads, plus build directions for the Black-Scholes-Merton formula.
Authored by shuo-li (Intel) Last updated on 01/26/2017 - 00:49
Article

Monte Carlo Method for Stock Options Pricing Sample

Download for Windows*

Authored by Vadim Kartoshkin (Intel) Last updated on 01/26/2017 - 00:49
Article

Data Layout Optimization Using SIMD Data Layout Templates

Financial service customers need to improve financial algorithmic performance for models such as Monte Carlo, Black-Scholes, and others. SIMD programming can speed up these workloads. In this paper, we perform data layout optimizations using two approaches on a Black-Scholes workload for European options valuation from the open source Quantlib library.
Authored by Nimisha R. (Intel) Last updated on 01/26/2017 - 00:49
Article

Intel® HPC Developer Conference 2016 - Session Presentations

The 2016 Intel® HPC Developer Conference brought together developers from around the world to discuss code modernization in high-performance computing.

Authored by Mike P. (Intel) Last updated on 01/26/2017 - 00:49
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Authored by David Mulnix (Intel) Last updated on 01/17/2017 - 10:09
Article

Heterogeneous STAC-A2* on the Intel® Xeon® Processor and Intel® Xeon Phi™ Coprocessor

STAC-A2 is a set of specifications defined by leading financial institutions, academia, and hardware vendors to represent realistic market risk analysis workloads. This article describes testing that measured the performance scaling of a system consisting of two Intel® Xeon® processors E5-2697 v3 and two Intel® Xeon Phi™ coprocessors 7120P or Intel® Xeon Phi™ processor 7250 and running the...
Authored by Robert Geva (Intel) Last updated on 12/15/2016 - 15:11
Article

Webcast: Parallel computing on Intel® Architecture

Regulatory pressures, which increase the amount of required computing, the need to improve operational efficiency and competition, which require faster computing,  are among the drivers that incent

Authored by Robert Geva (Intel) Last updated on 12/15/2016 - 15:03
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