Blog post

Hybrid MPI and OpenMP* Model

In the High Performance Computing (HPC) area, parallel computing techniques such as MPI, OpenMP*, one-sided communications, shmem, and Fortran coarray are widely utilized. This blog is part of a series that will introduce the use of these techniques, especially how to use them on the Intel® Xeon Phi™ coprocessor. This first blog discusses the main usage of the hybrid MPI/OpenMP model.
Authored by Nguyen, Loc Q (Intel) Last updated on 07/06/2019 - 17:10
Blog post

Mixing MPI and OpenMP*, Hugging Hardware and Dealing With It

This morning, I took a rare break, and attended a tutorial at Supercomputing.  I'm glad I did.

Authored by James R. (Blackbelt) Last updated on 07/06/2019 - 17:00
Blog post

Modernizing Software with Future-Proof Code Optimizations

by Henry A. Gabb, Sr. Principal Engineer, Intel Software and Services Group

Authored by Henry Gabb (Intel) Last updated on 07/06/2019 - 17:10
Blog post

N-Body Simulation Project at Cal Poly

The goal of the N-Body problem is to predict the motion of a set of n objects interacting with each other by some force, e.g. the gravitational force. N-Body simulations have been used in particles simulation such as astrophysical and molecular dynamics simulations. There are a number of approaches for solving the N-Body problem, such as the Barnes-Hut algorithm, the Fast Multipole method, the...
Authored by Nguyen, Loc Q (Intel) Last updated on 03/21/2019 - 12:08
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Knights Corner: Open source software stack

Knights Corner: Open source software stack

Authored by James R. (Blackbelt) Last updated on 07/06/2019 - 16:40
Blog post

Open Source Software Drives HPC Innovation

We’re on t

Authored by Robert W. (Intel) Last updated on 03/21/2019 - 12:00
Blog post

Fortran is more popular than ever; Intel makes it FAST

Just this past week, a senior radio telescope astronomer told me about the shift from C++ back to Fortran in his corner of the world. It is all about efficiency.

Authored by James R. (Blackbelt) Last updated on 03/21/2019 - 12:00
Blog post

A Guide to Optimization Techniques for the Intel® MIC Architecture

A 3-part educational series on Optimization Techniques for the Intel® MIC Architecture is provided by Colfax Research. The series focuses on select topics on optimization of applications for Intel’s multi-core and manycore architectures (Intel® Xeon® processors and Intel® Xeon Phi™ processors).
Authored by Iman S. (Intel) Last updated on 07/06/2019 - 16:40
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BKMs on the use of the SIMD directive

We had an ask from one of the various "Birds of a Feather" meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences.

Authored by Last updated on 07/06/2019 - 17:00
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Applying Intel® Threading Building Blocks Observers for Thread Affinity on Intel® Xeon Phi™ Coprocessors

In spite of the fact that the Intel® Threading Building Blocks (Intel® TBB) library [1] [2] provides high-level task based parallelism intended to hide sof

Authored by Alex (Intel) Last updated on 07/06/2019 - 17:00