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N-Body Simulation Project at Cal Poly

The goal of the N-Body problem is to predict the motion of a set of n objects interacting with each other by some force, e.g. the gravitational force. N-Body simulations have been used in particles simulation such as astrophysical and molecular dynamics simulations. There are a number of approaches for solving the N-Body problem, such as the Barnes-Hut algorithm, the Fast Multipole method, the...
Authored by Nguyen, Loc Q (Intel) Last updated on 03/21/2019 - 12:08
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Knights Corner: Open source software stack

Knights Corner: Open source software stack

Authored by James R. (Blackbelt) Last updated on 07/06/2019 - 16:40
Blog post

A Guide to Optimization Techniques for the Intel® MIC Architecture

A 3-part educational series on Optimization Techniques for the Intel® MIC Architecture is provided by Colfax Research. The series focuses on select topics on optimization of applications for Intel’s multi-core and manycore architectures (Intel® Xeon® processors and Intel® Xeon Phi™ processors).
Authored by Iman S. (Intel) Last updated on 07/06/2019 - 16:40
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BKMs on the use of the SIMD directive

We had an ask from one of the various "Birds of a Feather" meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences.

Authored by Last updated on 07/06/2019 - 17:00
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Applying Intel® Threading Building Blocks Observers for Thread Affinity on Intel® Xeon Phi™ Coprocessors

In spite of the fact that the Intel® Threading Building Blocks (Intel® TBB) library [1] [2] provides high-level task based parallelism intended to hide sof

Authored by Alex (Intel) Last updated on 07/06/2019 - 17:00
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Migrating Fortran Projects to the Intel® Xeon Phi™ Coprocessor

This article focuses on aspects of porting Fortran codes to the Intel® Xeon Phi™ coprocessor.  Most of the documentation for the coprocessor is C/C++ centric.

Authored by Last updated on 06/17/2019 - 15:47
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TACC symposium and programming two SMP-on-a-chip devices

Real results for many-core processors illustrate the power of a familiar configuration (SMP) even when reduced to a single chip.

Authored by James R. (Blackbelt) Last updated on 03/21/2019 - 12:08
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Knights Corner Micro-Architecture Support

How does a high performance SMP on-a-chip sound to you?

Authored by James R. (Blackbelt) Last updated on 07/06/2019 - 16:40
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MPI One-Sided Communication

In this continuation of the blog, Hybrid MPI and OpenMP* Model, I will di

Authored by Nguyen, Loc Q (Intel) Last updated on 07/06/2019 - 17:10