Article

Scale-Up Implementation of a Transportation Network Using Ant Colony Optimization (ACO)

In this article an OpenMP* based implementation of the Ant Colony Optimization algorithm was analyzed for bottlenecks with Intel® VTune™ Amplifier XE 2016 together with improvements using hybrid MPI-OpenMP and Intel® Threading Building Blocks were introduced to achieve efficient scaling across a four-socket Intel® Xeon® processor E7-8890 v4 processor-based system.
Authored by Sunny G. (Intel) Last updated on 12/12/2018 - 18:08
File Wrapper

Parallel Universe Magazine - Issue 27, January 2017

Authored by admin Last updated on 03/21/2019 - 12:00
Article

Maximize TensorFlow* Performance on CPU: Considerations and Recommendations for Inference Workloads

This article will describe performance considerations for CPU inference using Intel® Optimization for TensorFlow*
Authored by Nathan Greeneltch (Intel) Last updated on 04/01/2019 - 13:01
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Authored by Last updated on 03/25/2019 - 14:04
Article

Building and Probing Prolog* with Intel® Architecture

This article explores what happens when Intel solutions support functional and logic programming languages that are regularly used for Artificial Intelligence (AI) and proposes a Prolog interpreter recompilation using Intel® C++ Compiler and libraries in order to evaluate their contribution to logic based AI.
Authored by Flavio Luis de Mello Last updated on 01/24/2018 - 15:35
Article

Benefits of Intel® Optimized Caffe* in comparison with BVLC Caffe*

Overview
Authored by JON J K. (Intel) Last updated on 05/30/2018 - 07:00
Article

Understanding NUMA using Intel® Optimization for Caffe*

Introduction
Authored by Sunny G. (Intel) Last updated on 05/08/2018 - 09:38
Article

Recipe: ROME1.0/SML for the Intel® Xeon Phi™ Processor 7250

This article provides a recipe for how to obtain, compile, and run ROME1.0 SML on Intel® Xeon® processors and Intel® Xeon Phi™ processors.
Authored by Yu-Ping Z. (Intel) Last updated on 03/21/2019 - 12:00
Article

Intel® HPC Developer Conference 2016 - Session Presentations

The 2016 Intel® HPC Developer Conference brought together developers from around the world to discuss code modernization in high-performance computing.

Authored by Mike P. (Intel) Last updated on 03/21/2019 - 12:00