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Is there an IPP function to detect the processor type?

It describes how to use new Intel IPP function ippGetCpuFeatures() to retrieve processor features.
Authored by Ying Song (Intel) Last updated on 08/15/2016 - 08:23
Article

Understanding CPU Dispatching in the Intel® IPP Libraries

It lists all support CPUs and Identifiers used in Intel IPP.
Authored by admin Last updated on 09/01/2016 - 00:08
Article

Intel® IPP - Threading / OpenMP* FAQ

This page contains common questions and answers on multi-threading in the Intel IPP.
Authored by Naveen Gv (Intel) Last updated on 05/06/2016 - 16:41
Article

Using the performance tool to measure Intel IPP Function performance

This page explains how to use the Intel IPP performance test tool to measure the Intel IPP functions' performance
Authored by Ying Song (Intel) Last updated on 03/31/2016 - 22:48
Article

Intel® Compiler Options for Intel® SSE and Intel® AVX generation (SSE2, SSE3, SSSE3, ATOM_SSSE3, SSE4.1, SSE4.2, ATOM_SSE4.2, AVX, AVX2, AVX-512) and processor-specific optimizations

Explains which Intel® Compiler switches to use to target and optimize for a specific platform, microarchitecture, CPU or processor.
Authored by Martyn Corden (Intel) Last updated on 11/22/2016 - 09:51
Article

Intel® IPP Memory Function ippMalloc/Free FAQ

Information about Intel® IPP Memory functions
Authored by Naveen Gv (Intel) Last updated on 09/01/2016 - 00:08
Article

Intel® Fortran Compiler - Training courses

Authored by admin Last updated on 02/14/2016 - 10:19
Article

Intel® Fortran Compiler - Intel® IA-32 processor targeting options

There are two types of processor-specific optimization options:
Authored by admin Last updated on 02/14/2016 - 10:19
Article

Intel® Compiler - How can I generate optimized code to run on any IA-32 or Intel®64 architecture processor?

Some frequently used optimization switches of the Intel Compiler are described
Authored by admin Last updated on 02/14/2016 - 10:19
For more complete information about compiler optimizations, see our Optimization Notice.