4314 Matching Results
Forum topic

MICs appear to crash

I'm trying to setup a new system:

SuperMicro 5018GR-T

2 Intel Xeon Phis:

Authored by Orion P. Last updated on 05/28/2015 - 10:58

Sample Tweaker: Ocean Fog

This paper describes how we successfully optimized an existing graphics demo, named Ocean Fog, for our latest processors with Intel® Processor Graphics to achieve a 4x performance boost. Performance analysis was done using Intel® GPA.
Authored by Jeff Laflam (Intel) Last updated on 11/14/2014 - 11:10

How to manually target 2nd and 3rd generation Intel® Core™ processors with support for Intel® AVX

Manual cpu dispatch may be used to write code that will be executed only on Intel processors with support for Intel® Advanced Vector Extensions, such as 2nd generation Intel® Core™ processors (formerly code named “Sandy Bridge”), 3rd generation Intel® Core™ processors (formerly code named "Ivy Bridge") or future processors with support for Intel Advanced Vector Extensions 2..
Authored by Martyn Corden (Intel) Last updated on 03/12/2013 - 10:12

Intel® ArBB Videos, Tutorials and Webinars

This video archive helps developers quickly get up to speed on basic Intel® ArBB topics and advanced coding techniques.
Authored by AmandaS (Intel) Last updated on 05/26/2015 - 16:37

Intel® MKL with Numpy, Scipy, Matlab, C#, Python, NAG and more

The following article explains on using Intel® MKL with Numpy/SciPy, Matlab, C#, Java, Python, NAG, Gromacs, Gnu Octave, PETSc, HPL, HPCC, IMSL etc.
Authored by Gennady Fedorov (Intel) Last updated on 07/30/2014 - 02:51

Intel ArBB Segregated Storage and Data Copies

This article will answer the question when and how many copies occur for the inputs and outputs of an Intel ArBB function.
Authored by Hans Pabst (Intel) Last updated on 07/31/2013 - 08:21

Estimating FLOPS using Event Based Sampling (EBS)

Intel® VTune™ Amplifier XE can be used to estimate the FLOPS achieved by any given application.
Authored by Levent (Intel) Last updated on 05/27/2015 - 05:25

Distributed memory coarray programs with process pinning

This article describes a method to compile and run a distributed memory coarray program using Intel® Fortran Compiler XE 12.0. An example using Linux* is presented.
Authored by Patrick Kennedy (Intel) Last updated on 09/29/2014 - 07:39

Free Speedup with Compiler Switches for Fast Math and Intel® Streaming SIMD Extensions

Compilation can utilize Intel® Streaming SIMD Extensions instructions to improve floating point performance even if the source code isn't set up for SIMD. This paper describes simple steps to enable Intel® SSE & recognize if your code is being optimized.
Authored by Stan Melax (Intel) Last updated on 11/07/2014 - 13:15

Don't Spill That Register - Ensuring Optimal Performance From Intrinsics

This article helps developers ensure their C/C++ code with intrinsics produces the optimal assembly and shows how to spot unnecessary register spilling.
Authored by Stan Melax (Intel) Last updated on 11/03/2014 - 12:34
For more complete information about compiler optimizations, see our Optimization Notice.