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Parallel Universe Magazine - Issue 27, January 2017

Authored by admin Last updated on 03/21/2019 - 12:00
Article

Maximize TensorFlow* Performance on CPU: Considerations and Recommendations for Inference Workloads

This article will describe performance considerations for CPU inference using Intel® Optimization for TensorFlow*
Authored by Nathan Greeneltch (Intel) Last updated on 04/01/2019 - 13:01
Article

Caffe* Optimized for Intel® Architecture: Applying Modern Code Techniques

This paper demonstrates a special version of Caffe* — a deep learning framework originally developed by the Berkeley Vision and Learning Center (BVLC) — that is optimized for Intel® architecture.
Authored by Last updated on 07/06/2019 - 16:40
Article

Benefits of Intel® Optimized Caffe* in comparison with BVLC Caffe*

Overview
Authored by JON J K. (Intel) Last updated on 05/30/2018 - 07:00
Article

Recipe: Optimized Caffe* for Deep Learning on Intel® Xeon Phi™ processor x200

The computer learning code Caffe* has been optimized for Intel® Xeon Phi™ processors. This article provides detailed instructions on how to compile and run this Caffe* optimized for Intel® architecture to obtain the best performance on Intel Xeon Phi processors.
Authored by Vamsi Sripathi (Intel) Last updated on 03/21/2019 - 12:40
Article

Transform Enterprise, HPC & AI, Accelerate Parallel Code

Authored by admin Last updated on 07/06/2019 - 16:15
Article

Set Up Intel® Software Optimization for Theano* and Supporting Tools

Get recipes for installing development tools and libraries on various platforms for the Python library.
Authored by Sunny G. (Intel) Last updated on 05/08/2018 - 10:50
Article

Intel® Processors for Deep Learning Training

On November 7, 2017, UC Berkeley, U-Texas, and UC Davis researchers published their results training ResNet-50* in a record time (as of the time of their publication) of 31 minutes and AlexNet* in a record time of 11 minutes on CPUs to state-of-the-art accuracy. These results were obtained on Intel® Xeon® Scalable processors (formerly codename Skylake-SP).
Authored by Andres Rodriguez (Intel) Last updated on 04/15/2018 - 23:05