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Exploring Intel® Transactional Synchronization Extensions with Intel® Software Development Emulator

Intel® Transactional Synchronization Extensions (Intel® TSX) is perhaps one of the most non-trivial extensions of instruction set architecture introduced in the 4th generation Intel® Cor

Authored by Roman Dementiev (Intel) Last updated on 06/14/2017 - 15:53
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Android*: Написание многопоточных приложений с помощью Intel® Threading Building Blocks

Совсем недавно мы рассматривали написание многопоточных приложений для магазина Windows

Authored by Vladimir Polin (Intel) Last updated on 06/14/2017 - 15:59
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Quick Start Guides Published for the Intel® Xeon Phi™ Coprocessor Expert User

This is a short notice to let you know that two new articles have been published for the Intel® Xeon Phi™ coprocessor: * Quick Start Guide: For the Intel Xeon Phi Coprocessor Administrator * Quick Start Guide: For the Intel Xeon Phi Coprocessor Developer The target of both of these guides is the expert user. Our assumption is that the expert user does not need to be told what to do, as he...
Authored by Taylor IoT Kidd Last updated on 06/14/2017 - 16:24
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BKMs on the use of the SIMD directive

We had an ask from one of the various "Birds of a Feather" meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences.

Authored by Taylor IoT Kidd Last updated on 06/14/2017 - 16:22
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Performance BKMs: Introduction and Super-secret Intel Tools

At SC13 (Super Computing 2013)*, someone commented that Intel seems to have some super-secret set of tricks in its pocket, allowing us to optimize “far beyond those of mortal man”+.

Authored by Taylor IoT Kidd Last updated on 06/14/2017 - 16:20
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Submissions open: High Performance Parallelism Gems

We have all had our little discoveries and triumphs in identifying new and innovative approaches that increased the performance of our applications. Occasionally we find something more, something that could also help others, an innovative gem. You now have an opportunity to broadcast your successes more widely to the benefit of our community. You are invited to submit a proposal to a...
Authored by Taylor IoT Kidd Last updated on 01/24/2018 - 12:12
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Webinar: Programmer's Guide to Knights Landing

The Intel’s next generation Xeon Phi™ processor family x200 product (code-name Knights Landing) brings in several new technological solutions: socket form-factor (stand-alone CPU), as well as coprocessor version; a high bandwidth on package memory called Multi-Channel DRAM (MCDRAM) in addition to the traditional DDR4, which leads to three modes of MCDRAM operation - cache, flat, and hybrid;...
Authored by Vadim K. (Intel) Last updated on 06/14/2017 - 16:15
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Brain Development Simulation, 300x Faster

Authored by Andrey Vladimirov Last updated on 07/17/2017 - 17:03
For more complete information about compiler optimizations, see our Optimization Notice.