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Intel(R) Manycore Platform Software Stack (MPSS) - Long-Term-Support Archive

In this page you will find the last releases of the Intel(R) Manycore Platform Software Stack (MPSS) Long Term Support product (LTS). The most recent release is found here: http://software.intel.com/en-us/articles/intel-many-integrated-core-architecture-intel-mic-architecture-platform-software-stack and we recommend customers use the latest release wherever possible.
Authored by Nguyen, Loc Q Last updated on 01/17/2017 - 16:42
Article

Intel® Xeon® Processor E5-2600 V4 Product Family Technical Overview

The Intel® Xeon® processor E5-2600 v4 product family, code-named Broadwell EP, is a two-socket platform based on Intel’s most recent microarchitecture. Intel uses a “tick-tock” model associated with its generation of processors. This new generation is a “tick” based on 14nm process technology. Major architecture changes take place on a “tock,” while minor architecture changes and a die shrink...
Authored by David Mulnix (Intel) Last updated on 01/17/2017 - 10:09
Article

Using Intel® Data Analytics Acceleration Library to Improve the Performance of Naïve Bayes Algorithm in Python*

This article discusses machine learning and describes a machine learning method/algorithm called Naïve Bayes (NB) [2]. It also describes how to use Intel® Data Analytics Acceleration Library (Intel® DAAL) [3] to improve the performance of an NB algorithm.
Authored by Nguyen, Khang T Last updated on 01/17/2017 - 10:04
Article

Fast Computation of Huffman Codes

The generation of Huffman codes is used in many applications, among them the DEFLATE compression algorithm. The classical way to compute these codes uses a heap data structure. This approach is fairly efficient, but traditional software implementations contain lots of branches that are data-dependent and thus hard for general-purpose CPU hardware to predict. On modern processors with deep...
Authored by James Guilford (Intel) Last updated on 01/17/2017 - 09:53
Video

Respect Programming Models – Manage Intel® Xeon Phi™ in your Clusters for Enhanced User Experience

High performance computing (HPC) cluster programming model number 1 has been MPI for the past 10 or more years.

Authored by admin Last updated on 01/12/2017 - 16:13
Video

Fast, lightweight, scalable MPI performance analysis

Developers of modern high performance computing (HPC) applications face a challenge when scaling out their hybrid (MPI/OpenMP*) applications.

Authored by admin Last updated on 01/12/2017 - 16:11
Video

Parallel Program Model on Intel® Xeon and Intel® Xeon Phi™ coprocessor

Upon completion of this webinar, you will be familiar with parallel programming models and their optimized use on clusters of Intel® Xeon and Intel® Xeon Phi™ coprocessor.

Authored by admin Last updated on 01/12/2017 - 16:04
Video

Think Parallel Modern Applications for Modern Hardware

High performance computing (HPC) codes have used MPI and similar models to scale to multiple nodes, but increasingly parallelism is also required within a node, and even within a single core.

Authored by admin Last updated on 01/12/2017 - 16:03
Video

"Correct" to "Correct and Efficient": A Case Study with Hydro2D

Upon completion of this webinar, you will be familiar with how a given physical process be simulated on a computer efficiently.

Authored by admin Last updated on 01/12/2017 - 15:58
Video

An Introduction to Intel® Visual Fortran Development on Intel® Xeon Phi™ coprocessor

The Intel® Visual Fortran Composer XE SP1 release includes support for Intel® Xeon Phi™ coprocessors on Windows*.

Authored by Kevin D (Intel) Last updated on 01/12/2017 - 15:32
For more complete information about compiler optimizations, see our Optimization Notice.