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Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family

A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
Authored by Khang N. (Intel) Last updated on 05/05/2016 - 10:59
Video

Taking on STEM education and (em)power(ed) positions

Prabha Ganapathy relates her experience as a girl growing up in India, and the influence that Indian emphasis on STEM education had on her.

Authored by admin Last updated on 05/05/2016 - 10:58
Forum topic

Converting Application to mobile application

I am designing a web application and am looking forward to converting it directly to mobile app for android .Apk blackberry and ios.

what are my alternatives pls?

Authored by Adeola I. Last updated on 05/05/2016 - 10:54
Video

A Step by Step Guide to Building LittleFe

This is a step by step guide to builidng LittleFe, a complete 6 node Beowulf style portable computational cluster.

To learn more visit http://littlefe.net/home

Authored by Jerry Makare (Intel) Last updated on 05/05/2016 - 11:07
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 4

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/05/2016 - 11:08
Video

Beginning Intel Xeon Phi Coprocessor Workshop: Programming Modeling Part 3

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Jerry Makare (Intel) Last updated on 05/05/2016 - 11:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 2

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/05/2016 - 11:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Performance Analysis

This module briefly discusses a performance analysis methodology, collecting HW performance data  and using Intel® VTune Applifier XE to view and interpret the performance data.

Authored by Taylor K. (Intel) Last updated on 05/05/2016 - 11:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Modeling Part 1

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/05/2016 - 11:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Optimization Part 2

This module looks at basic optimization techniques for the Intel Xeon Phi coprocessor.

Authored by Taylor K. (Intel) Last updated on 05/05/2016 - 11:08
For more complete information about compiler optimizations, see our Optimization Notice.