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floating point precision

Using Intel's i5 and i7 hardware, would a double precision ieee format be better utilized with a REAL( kind = 10 ) rather than a REAL ( kind = 8 ) format.

Authored by Brooks V. Last updated on 05/30/2016 - 13:55
Forum topic

PCIe peer-to-peer transactions

We are trying to make a peer-to- peer transaction between 2 End-Points, through Intel chipset without succession. (Not through CPU/ CPU memory).

Authored by Itai A. Last updated on 05/30/2016 - 13:53
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 4

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/30/2016 - 14:08
Video

Beginning Intel Xeon Phi Coprocessor Workshop: Programming Modeling Part 3

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Jerry Makare (Intel) Last updated on 05/30/2016 - 14:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Models Part 2

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/30/2016 - 14:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Performance Analysis

This module briefly discusses a performance analysis methodology, collecting HW performance data  and using Intel® VTune Applifier XE to view and interpret the performance data.

Authored by Taylor K. (Intel) Last updated on 05/30/2016 - 14:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Programming Modeling Part 1

This module looks at the rationale behind the approach taken by Intel with regards to the Intel® Xeon Phi coprocessor HW abstraction, programming model options, using standardized libraries such as

Authored by Taylor K. (Intel) Last updated on 05/30/2016 - 14:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Optimization Part 2

This module looks at basic optimization techniques for the Intel Xeon Phi coprocessor.

Authored by Taylor K. (Intel) Last updated on 05/30/2016 - 14:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Optimization Part 1

This module looks at basic optimization techniques for the Intel Xeon Phi coprocessor.

Authored by Taylor K. (Intel) Last updated on 05/30/2016 - 14:08
Video

Beginning Intel® Xeon Phi™ Coprocessor Workshop: Advanced Offload Topics Part 3

This module is a more in depth discussion of the offload programming model.

Authored by Taylor K. (Intel) Last updated on 05/30/2016 - 14:08
For more complete information about compiler optimizations, see our Optimization Notice.