AES New Instructions
- Intel® AES New Instructions (Intel® AES-NI)
Overview of Intel® AES-NI, a new encryption instruction set that improves on the Advanced Encryption Standard (AES) algorithm and accelerates the encryption of data.
- Securing the Enterprise with Intel® AES-NI
Learn why cryptography is hot in the marketplace today, especially in the enterprise.
- Intel® Advanced Encryption Standard Instructions (AES-NI)
Description of the six new instructions that make up the AES-NI instruction set and perform several compute intensive parts of the AES algorithm.
Digital Random Number Generator
- Bull Mountain is Intel's code name for its new Intel® 64 Architecture instruction RdRand and its underlying Digital Random Number Generator (DRNG) hardware implementation. Bull Mountain provides a processor-based RNG solution that is of high quality and performance, highly available, and secure.
Intel Instruction Set Architecture Extensions
- Intel® Memory Protection Extensions (Intel® MPX) is a name for Intel Architecture extensions designed to increase robustness of software
- Software Guard Extensions (SGX) is a name for Intel Architecture extensions designed to increase the security of software through an “inverse sandbox” mechanism
- Intel® Secure Hash Algorithm Extensions (Intel® SHA) are a family of seven Intel® Streaming SIMD Extensions (Intel® SSE)-based instructions that are used together to accelerate the performance of SHA-1 and SHA-256 on Intel architecture-based processors
This document describes the Intel® Active Management Technology (Intel® AMT) Release 1.0 Host Information Interface APIs, which are provided to Independent Software Vendors (ISV) for their applications. These APIs allow an ISV application to collect information about Intel AMT in the “OS-present”...
Intel® Active Management Technology (Intel® AMT), starting with Release 2.0 provides for a standard and single-sign-on style of authentication by integrating its authentication framework with Microsoft Windows* Active Directory. This document provides an overview of Kerberos, a description of the...
Intel® Active Management Technology (Intel® AMT) Release 2.5 and later releases can generate posture messages that are compatible with the Cisco* Network Admission Control (NAC) system. In support of this feature, the Intel® vPro™ Kit includes a NAC Posture Plug-In that, in conjunction with a Cis...
Jump start your software development for the soon to be released Intel® Core™2 processor with vPro™ technology (codenamed: McCreary). Get an overview of the Intel Active Management Technology (Intel AMT) and all new features in the Intel AMT 4.0/5.0. Register for this free event and take advantag...
Intel® Virtualization Technology (Intel® VT)
- Virtualization HW technical brief
Intel Virtualization Technology (Intel VT) provides comprehensive hardware assists that boost virtualization software performance, improve application response times and provide greater reliability, security and flexibility.
- Virtualization: A Developer's Friend
The more developers use virtualization, the more they find new uses for it. Discover what you’re missing and how virtualization can help you get more done.
- Intel® Virtualization Technology: Flash* Animation
This animation provides an overview of Intel® Virtualization Technology, which is a technique by which hardware resources can be abstracted, divided, and shared between multiple operating system environments running simultaneously.
- Intel® Virtualization Technology: Best Practices for Software Vendors
This series of articles functions as an aid to help software vendors tailor their applications for use with Intel VT.
During vmlaunch/vmresume, several checks are performed on the guest state area. I was wondering if anyone else had noticed that Guest RSP field is never checked for a non-canonical address. The virtualization spec talks about such checks for Guest RIP or GDTR or IDTR. I was wondering why this check was not done for the Guest RSP?
By Yogi D.1
Hi. I am writing a small OS-agnostic hypervisor as a teaching tool for my students. The hypervisor code is loaded by the code I embed in a custom MBR on the boot device when the system boots. The hypervisor code switches to 32-bit proected mode and then IA32e (64-bit mode). It then sets up the hypevisor, EPT to protect the hypervisor from the guests, and launches a 16-bit "unrestricted" big real-mode (or unreal mode) guest. All this is working perfectly. The guest can make BIOS calls. The hypervisor writes directly to the video buffer in order to provide debugging/status info. The hypervisor is setup to VMexit minimally (e.g., I/O, APIC, MSRs, etc. are not monitored -- yet). When the real-mode guest causes EPT violations, issues CPUID, etc. these cause VMExits as expected and the hypervisor handles them and resumes the guests. When the 16-bit guest issues an INIT IPI to itself using the APIC, I run into an infinite VMExit situation that my hypervisor cannot seem to recover ...
By Tyler T.0
There is additionally an e-book which food the entirety Forever Body Transformation review, and with the aim of indicates you will certainly recognize I beg your pardon? To expect and exactly how to stipulate your very own goals. Using their Forever Body Transformation Plan, they will expound recently I beg your pardon? Dishes is really Pro-FBT and specifically I beg your pardon? Foods are normally Anti-FBT and the instrument to sustain your metabolic value operating in ideal degrees. And additionally the wonderful feature pertaining toForever Body Transformation is the actuality with the aim of it comes having a 60 days 100 % money back ensure assure, so you possibly will test it away instead of a few kind of complete sixty days and additionally return this in issue it is not in point of fact instead of you personally. Forever Body Transformation is a emphasis loss list with the aim of might aid folks who are having problems of being round. That imply with the aim of every time a a...
By Tracy Camp1
I'm aware that software can check the IA32_VMX_EPT_VPID_CAP MSR to determine if the EPT table supports access and dirty bits... However I would like to know how to identify a processor before I've purchased it that has this support. This is a common frustration I have with Intel parts - minor features vary quite a bit and don't seem to necissarily 'stick' in a linear progression of CPUID values due to various market differentiations. Most of the time it doesn't matter too much, since most features are just an optimization for something that doesn't need to be implemented in software, however in this particular case, I'm not sure how to 'emulate' the lack of an accessed and dirty bit in the EPT tables of earlier EPT implementations in software.
By Hitesh Prajapati1
Dear Sir/Madam, We have intel 10GbE Network Adapter X540-T2. Please guide me for the virtualization testing software for the adapter. I am new to this forum, also guide me that is this correct forum for the 10GbE network Adapter X540-T2. Reply me as early as possible. Thanks in advacne.
By Ralf H.1
Hi, we're currently working in a project that involves extending the KVM hypervisor. While running the VM, we sometimes get EPT violations that shouldn't be possible from our understanding of the Intel documents. The scenario is as follow (we use Intel VT with EPT enabled):All guest paging structures (i.e., the paging structures _inside_ the VM) are set to non-writable on the last EPT level. In other words, whenever the guest OS writes to a guest paging structure (e.g. to map/free a page), this triggers an EPT violation. Now, "occasionally" the following happens:The VM performs a normal read operation somewhere in memory (doesn't seem to matter where). This then yields an EPT violation and bit 0, bit 1, and bit 7 are set in the exit qualification field, bit 8 is cleared. According to the Intel specification (Table 27-7), this means that the EPT violation was caused by the MMU setting the dirty or accessed bit in the guest paging structures. At first, this makes sense since these ar...
Rather than force a user to abruptly break away from routines that have become easy to perform, I think it might be a good idea to run Windows 7 in a virtual environment on the new platform; provided it is possible to hotkey from the new work environment to the old, and back to the new in a New York minute. My interest in this came about when after changing from an old fashion notebook to an Ultraboook with a Touch screen I discovered the Start menu has changed, of course. Also, I realized that using a slow browser on a fast platform doesn’t make sense, so I left behind my beloved IE8 with iGoogle homepage and changed to speedy Google Chrome. Then I found myself wondering how to save Favorites, block pop-ups, establish and maintain trust relations, all things I had become somewhat familiar with doing, and now have to consciously think about again. I am looking forward to making greater use of audio and video processing capabilities in the new 64-bit environment. Since A/V file...
By Michael L.1
Hi, From what I understand, the VMX-preemption timer should only decrement when in VMX non-root operations. I have been trying to use it as a way to measure cycle time in a VM, with respect to the running time of that VM. Hence, I do not want to include in my measurement the time spent in the VMM or the time to perform VM entries/exits. VMX-preemption timer seems like it could serve that purpose (with the granularity of the TSC to VMX-preemption timer ratio). However, in my test, the VMX-preemption timer seems to also decrement while performing VM entry/exits. My test: a) from the VMM: read the VMX-preemption timer in the VMCS b) VM enter c) VM exit *immediately after VM enter* (eip set to the hlt instruction) d) from the VMM: read the VMX-preemption timer in the VMCS (processor setup to save the VMX-preemption timer to VMCS on VM exit) the difference between (d) and (a) should be zero or a very small value since the VMX-preemption timer should only be decrementing when executing i...