AES New Instructions
- Intel® AES New Instructions (Intel® AES-NI)
Overview of Intel® AES-NI, a new encryption instruction set that improves on the Advanced Encryption Standard (AES) algorithm and accelerates the encryption of data.
- Securing the Enterprise with Intel® AES-NI
Learn why cryptography is hot in the marketplace today, especially in the enterprise.
- Intel® Advanced Encryption Standard Instructions (AES-NI)
Description of the six new instructions that make up the AES-NI instruction set and perform several compute intensive parts of the AES algorithm.
Digital Random Number Generator
- Bull Mountain is Intel's code name for its new Intel® 64 Architecture instruction RdRand and its underlying Digital Random Number Generator (DRNG) hardware implementation. Bull Mountain provides a processor-based RNG solution that is of high quality and performance, highly available, and secure.
Intel Instruction Set Architecture Extensions
- Intel® Memory Protection Extensions (Intel® MPX) is a name for Intel Architecture extensions designed to increase robustness of software
- Software Guard Extensions (SGX) is a name for Intel Architecture extensions designed to increase the security of software through an “inverse sandbox” mechanism
- Intel® Secure Hash Algorithm Extensions (Intel® SHA) are a family of seven Intel® Streaming SIMD Extensions (Intel® SSE)-based instructions that are used together to accelerate the performance of SHA-1 and SHA-256 on Intel architecture-based processors
By Ajith Illendula (Intel)Posted 04/13/20110
Intel® Active Management Technology Use Case #12:Fast Call for Help Fast Call for Help aka Client Initiated Remote Access (CIRA) feature of Intel® Active Management Technology (Intel® AMT) allows Intel® vPro™ technology platforms to initiate a secured connection to a gateway server residing in th...
Intel® AMT SCSDiag Utility Enables debugging of the Setup and Configuration Service – SCS and its database. Connects to the SCS database and collects debug and ongoing DB data. Ultimately assists in helping to provide debugging and maintenance assistance for the SCS and the SCS DB. Automatica...
Intel® AMT SCSDiag utility enables debugging of the Setup and Configuration Service – SCS and its database, and connects to the SCS database and collects debug and ongoing DB data.
This presentation introduces Intel® Active Management Technology (Intel® AMT) Setup and Configuration Service (SCS). SCS is the process by which Intel® AMT features are made available to Management Consoles / Applications.
Intel® Virtualization Technology (Intel® VT)
- Virtualization HW technical brief
Intel Virtualization Technology (Intel VT) provides comprehensive hardware assists that boost virtualization software performance, improve application response times and provide greater reliability, security and flexibility.
- Virtualization: A Developer's Friend
The more developers use virtualization, the more they find new uses for it. Discover what you’re missing and how virtualization can help you get more done.
- Intel® Virtualization Technology: Flash* Animation
This animation provides an overview of Intel® Virtualization Technology, which is a technique by which hardware resources can be abstracted, divided, and shared between multiple operating system environments running simultaneously.
- Intel® Virtualization Technology: Best Practices for Software Vendors
This series of articles functions as an aid to help software vendors tailor their applications for use with Intel VT.
By Stephen Smith (Intel)Posted 10/02/20080
IntroductionVirtualization has become ubiquitous in general IT datacenter environments. Existing applications are already being run in production virtualized modes today with many more running virtualized in non-production testing environments.In some cases, this situation has arisen without the...
By kenstrandbergPosted 09/30/20081
By Ken Strandberg Contents Introduction Core Effects 64-bit Deployments Processor Optimization Hyper-Threading Processor Affinity No Affinity Pinned VMware Virtual SMP* Memory VMware Resource Pools, Shares, Reservations, and Limits Storage and Virtual Machines Conclusion Introduction Optimi...
Performance Impacts with Optimized Virtual Environments on Intel® Virtualization Technology-based Platforms
Contents Overview Benchmark Tests Benchmark Test Suite Explanation SPECjbb SysBench Test Modes Terminology Benchmark Results Test Environment 1 SysBench Results SPECjbb Results Test Environment 2 – SPECjbb Results: SPECjbb2005 Test Environment 3 – SysBench Results: SQL Server 2005 OLTP Conc...
By binstockPosted 09/09/20083
The more developers use virtualization, the more they find new uses for it. Discover what you’re missing and how virtualization can help you get more done. by Andrew Binstock Many developers today are finding that virtualization enables them to develop, test, and debug software in ways they ne...
By Hitesh Prajapati1
Dear Sir/Madam, We have intel 10GbE Network Adapter X540-T2. Please guide me for the virtualization testing software for the adapter. I am new to this forum, also guide me that is this correct forum for the 10GbE network Adapter X540-T2. Reply me as early as possible. Thanks in advacne.
By Ralf H.1
Hi, we're currently working in a project that involves extending the KVM hypervisor. While running the VM, we sometimes get EPT violations that shouldn't be possible from our understanding of the Intel documents. The scenario is as follow (we use Intel VT with EPT enabled):All guest paging structures (i.e., the paging structures _inside_ the VM) are set to non-writable on the last EPT level. In other words, whenever the guest OS writes to a guest paging structure (e.g. to map/free a page), this triggers an EPT violation. Now, "occasionally" the following happens:The VM performs a normal read operation somewhere in memory (doesn't seem to matter where). This then yields an EPT violation and bit 0, bit 1, and bit 7 are set in the exit qualification field, bit 8 is cleared. According to the Intel specification (Table 27-7), this means that the EPT violation was caused by the MMU setting the dirty or accessed bit in the guest paging structures. At first, this makes sense since these ar...
Rather than force a user to abruptly break away from routines that have become easy to perform, I think it might be a good idea to run Windows 7 in a virtual environment on the new platform; provided it is possible to hotkey from the new work environment to the old, and back to the new in a New York minute. My interest in this came about when after changing from an old fashion notebook to an Ultraboook with a Touch screen I discovered the Start menu has changed, of course. Also, I realized that using a slow browser on a fast platform doesn’t make sense, so I left behind my beloved IE8 with iGoogle homepage and changed to speedy Google Chrome. Then I found myself wondering how to save Favorites, block pop-ups, establish and maintain trust relations, all things I had become somewhat familiar with doing, and now have to consciously think about again. I am looking forward to making greater use of audio and video processing capabilities in the new 64-bit environment. Since A/V file...
By Michael L.1
Hi, From what I understand, the VMX-preemption timer should only decrement when in VMX non-root operations. I have been trying to use it as a way to measure cycle time in a VM, with respect to the running time of that VM. Hence, I do not want to include in my measurement the time spent in the VMM or the time to perform VM entries/exits. VMX-preemption timer seems like it could serve that purpose (with the granularity of the TSC to VMX-preemption timer ratio). However, in my test, the VMX-preemption timer seems to also decrement while performing VM entry/exits. My test: a) from the VMM: read the VMX-preemption timer in the VMCS b) VM enter c) VM exit *immediately after VM enter* (eip set to the hlt instruction) d) from the VMM: read the VMX-preemption timer in the VMCS (processor setup to save the VMX-preemption timer to VMCS on VM exit) the difference between (d) and (a) should be zero or a very small value since the VMX-preemption timer should only be decrementing when executing i...
no wonder it possible for professionals to adanay kalanagn desktop and server virtualization, but it is very confusing for the layman, because it is almost like it is just different in the context of network and local only.desktop virtualization is more focused on the dektop without touching the network between computers, such as, VMWare Player, Virtualbox, Qemu, etc.. very useful for testing the OS on the client.server virtualization is more directed to the network as it relates to the Internet or a network cable or wireless jaringn keuntunganya further test of seranagn hackers because networks are vulnerable from attacks hercker!no wonder it possible for professionals to adanay kalanagn desktop and server virtualization, but it is very confusing for the layman, because it is almost like it is just different in the context of network and local only.desktop virtualization is more focused on the dektop without touching the network between computers, such as, VMWare Player, Virtualbox...
Hi, i'm creating a hypervisor based on Intel-vt extensions, each VM must be able to have it's own hypervisor with Intel-vt (i don't have choice). The probleme is to use a hypervisor into a VM with Intel-VT require to be in root-operation to perfectly use virtualization instructions such as VMCALL, VMREAD ... But each vm-exit will only give control to the first hypervisor. So the sub-monitor will never be used. How can i do that ? Is nested virtualization with Intel-VT is realy possible without modifying guest ? Thanks a lot.
I'm trying to find out what does the Microsoft Hypervisor register for as its control fields. What registers do I need to be looking at it to find this? The documentaiton is unclear as to where the registers are that control the fields. It keeps saying bitmaps .. but to what.