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List of Useful Power and Power Management Articles, Blogs and References
By Taylor Kidd (Intel)Posted 04/17/20142
INTRODUCTION AND PURPOSE: This article endeavors to provide a single point of reference to Power Management blogs, articles and other resources relevant to the Intel® Xeon Phi™ coprocessor. There are many excellent resources out there on power, power management and tools; this article cannot ho...
Power Management States: P-States, C-States, and Package C-States
By Taylor Kidd (Intel)Posted 04/17/20140
(For a PDF version of this article, download the attachment.) Contents Preface: What, Why and from Where. 1 Chapter 1: Introduction and inquiring minds. 2 Chapter 2: P-States, Reducing power consumption without impacting performance. 3 Chapter 3: Core C-States, The Details. 5 Chapter 4: ...
Resolving Symbols for Intel® Manycore Platform System Stack (Intel® MPSS) in Intel® VTune™ Amplifier XE Analysis
By Sumedh Naik (Intel)Posted 04/09/20140
Background Whenever Intel VTune Amplifier XE is unable to resolve symbols for libraries or the operating system, it lumps all the counts for that module together. Often, these lumped counts end up at the top of the hotspot list, skewing the analysis. By setting the correct search library path in...
Recipe: Building and Optimizing the Hogbom Clean Benchmark for Intel® Xeon Phi™ Coprocessors
By Sumedh Naik (Intel)Posted 04/09/20140
Overview This article provides a recipe for compiling and running the Hogbom Clean benchmark for the Intel® Xeon Phi™ coprocessor and discusses the various optimizations applied to the code.  Introduction Hogbom Clean is a part of the ASKAP benchmark package. The ASKAP benchmark package is use...

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Go Parallel 2
By Dmitry VyukovPosted 04/13/20140
Parallel programming with Go language (golang). The blog shows examples of parallel divide-and-conquer decomposition and parallel pipelines.
Indexing the Mahabharata
By mecej41Posted 04/01/20140
by N. Shamsundar The Mahabharata may be compared to the Greek Iliad or the Persian Shahnameh. Such epics contribute considerably to the culture of a nation, provide a vehicle for learning national languages, and may provide background information on the dominant religion of the country. Now and...
Detecting Network-bound Applications in Server Systems
By loc-nguyen (Intel)Posted 03/29/20140
Following my previous blogs, Detecting CPU-bound Applications in Server Systems and Detecting Disk I/O-bound Applications in Server Systems, I will continue the discussion in this blog on detecting a network-bound application. When network I/O applications run, they can consume almost all avail...
Meshcentral.com - Second IP address
By ylian-saint-hilaire (Intel)Posted 03/28/20142
Just a quick note to say that a few days back, we added a second static IP address to Meshcentral.com and made it known as "swarm.meshcentral.com". I configured the server so that port 443 on the new IP address is identical to port 8080 on the original address. So, Mesh agents can now connect b...

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Instruction set extensions programming reference, revision 18
By Mark Charney (Intel)0
In early February, an updated instruction set extensions programming reference, revision 18, has been posted here.  It includes information about: Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions Intel® Secure Hash Algorithm (Intel® SHA) extensions  Intel® Memory Protection Extensions (Intel® MPX)  For more information about the technologies: http://www.intel.com/software/isa
Updated Intel® Software Development Emulator
By Ady Tal (Intel)0
Hello, we just released version 6.20 of the Intel® Software Development Emulator. It is available here:http://www.intel.com/software/sde It includes: Added support for XSAVEC and CLFLUSHOPT. Disabled TSX CPUID bits when TSX emulation is not requested. Improved disassembly for MPX instructions. Added an option for running chip-check only on the main executable. Added support for -quark (Pentium ISA). Added application debugging for Mac OSX with the lldb debugger.
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1
By kathy-farrel (Intel)0
Intel® Parallel Studio XE SP1 & Intel® Cluster Studio XE SP1 - What's New - Webinar Tuesday, September 17 9am PDT Please join us for a technical presentation on the new features found in the recently released Intel® Parallel Studio XE 2013 SP1 Intel® Cluster Studio XE SP1. This release includes support for compilers and performance analysis on Intel® Xeon Phi™ on Windows*. The technical presentation will briefly cover new features for both C++ and Fortran on Linux*, Windows*, and OS X* operating systems as well as error checking and performance profiling tools. Learn how to efficiently boost your application performance! Not too late! - Register Now  Learn about Upcoming Webinars
Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
By Roman Dementiev (Intel)4
Hi, you might find this collection of technical material about Intel TSX instructions useful: http://www.intel.com/software/tsx By a suggestion from some senior forum contributors I am making this post sticky. Best regards, Roman
Links to instruction documentation
By Thomas Willhalm (Intel)24
The Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A and 2B (available here) are the instruction set reference. Haswell (2013) new instructionsare in theprogrammer's reference manual. In appendix C of the Intel 64 and IA-32 Architectures Optimization Reference Manual (available here), the latencies and throughput of instructions are listed. The documentation of the Intel C++ Compiler contains documentation of the intrinsics. The AVX Programming Reference and examples for using AVX are available on the AVX community page. (The interactive Intel Intrinsics Guide is also available there, which is useful for SSE programming as well.) The Intel Software Development Emulator (Intel SDE) allows simulation of future instructions.
Locking CPU cache lines for a thread ( L1)
By Younis A.4
Hi I'm working on securing access to L1 cache by locking it line by line. Is there any way to do it? For example, two threads accessing the L1 and L1 lines are locked for a certain time to each thread accessed them. Regards, Younis
Problem when using RTM
By geomap0
Hello, My name is George Mappouras and I am trying to make a simple program in order to evaluate the TSX in the new Haswell processors. However I came across a very strange problem that I can't find its cause and I was wondering if you could help me with it. The idea is simple, I have 'x' accounts and 'n' threads. Each thread does 'k' amount of transactions between random accounts (I transfer a random amount from account1 to account2 ). I tried this program with RTM, spinlocks and mutex (fine grained locking). In the end I check my results by comparing them to a single threaded version of this program. The problem is that in the case of the RTM (with or without fallback path) I noticed that sometimes the results don't match the single-threaded results.  I also noticed that this seems to happen only when I use hyperthreading. (The computer in which I test my program has 4 physical cores with hyperthreading, that means 8 threads max). I tried to debug my program and I suspect that the...
asm blocks
By berthou4
Hello, I am writing AVX code inside asm blocks (don"t want to use avx intrinsics). A lot of gp registers are used and so they are mixed with the ones generated by the compiler and thus it is screwing the behavior of the code pretty fast. Is there an automatic or manual way to avoid these register overlaps ? Any link to documentation would be great. I would like also to use asm blocks in fortan with ifort, but didn't find the way yet. Thanks Vincent

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