HPC

Videos - Parallel Programming with Intel Xeon Phi Coprocessors

Here is a list of recently published videos from Colfax International on Intel(R) Xeon Phi(TM) Coprocessors.

In this video we will discuss software tools needed and recommended for developing applications for Intel Xeon Phi coprocessors. We will begin with software that is necessary to boot coprocessors and to run pre-compiled executables on them.

Videos - Parallel Programming and Optimization with Intel Xeon Phi Coprocessors

Here is a set of introductory videos from Colfax International on Parallel Programming and Optimization with Intel(R) Xeon Phi(TM) Coprocessors.

In this video episode we will introduce Intel Xeon Phi coprocessors based on the Intel Many Integrated Core, or MIC, architecture and will cover some of the specifics of hardware implementation.

Measuring Power on Intel® Xeon Phi™ Product Family Devices

Understanding power measurements and the issues associated with various power measurement methodologies is key to utilizing, procuring and deploying large HPC (High Performance Computing) clusters along with maximizing bottom line profit in the enterprise world. In the HPC space, large FLOPs/watt ratios are now a key design and procurement requirement as the operating costs of today’s petascale systems are on par with the acquisition costs of the actual supercomputer hardware itself (Subramaniam & Wu-chun, 2010).

  • Developers
  • Linux*
  • Server
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  • HPC
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  • KNL
  • Knights Landing
  • KNC
  • Intel® Many Integrated Core Architecture
  • Power Efficiency
  • Calculating “FLOP” using Intel® Software Development Emulator (Intel® SDE)

    Purpose

    Floating point operations (FLOP) rate is used widely by the High Performance Computing (HPC) community as a metric for analysis and/or benchmarking purposes. Many HPC nominations (e.g., Gordon Bell) require the FLOP rate be specified for their application submissions.

    The methodology described here DOES NOT rely on the Performance Monitoring Unit (PMU) events/counters. This is an alternative software methodology to evaluate FLOP using the Intel® SDE.

  • Developers
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  • Students
  • Linux*
  • Server
  • Advanced
  • Intermediate
  • Intel® Software Development Emulator
  • FLOP
  • Knight’s Landing
  • Intel® SDE
  • HPC
  • Floating point operations
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Core™ processor family
  • Intel® Many Integrated Core Architecture
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