HPC

Parallel Programming and Optimization with Intel® Xeon Phi™ Coprocessors Developer Training Event

The 1-day seminar (CDT 101) features presentations on the available programming models and best optimization practices for the Intel Xeon Phi coprocessor, and on the usage of the Intel software development and diagnostic tools. CDT 101 is a prerequisite for hands-on labs, CDT 102.

Videos - Parallel Programming with Intel Xeon Phi Coprocessors

Here is a list of recently published videos from Colfax International on Intel(R) Xeon Phi(TM) Coprocessors.

In this video we will discuss software tools needed and recommended for developing applications for Intel Xeon Phi coprocessors. We will begin with software that is necessary to boot coprocessors and to run pre-compiled executables on them.

视频 - 借助英特尔至强融核协处理器实现并行编程

Colfax International 最近发布了下列一组关于英特尔(R) 至强融核(TM) 协处理器的视频。

面向英特尔至强协处理器的软件工具
该视频主要介绍了开发面向英特尔至强融核协处理器的应用时所需要并推荐采用的软件工具。 我们首先介绍启动协处理器以及运行预编译的可执行文件所需的软件。

我的应用是否能受益于 MIC 架构
在本视频中,我们将探讨可在英特尔至强融核协处理器上有效运行的应用类型。 我希望上述介绍能够帮助大家回答“我的应用是否能受益于 MIC 架构?”

Videos - Parallel Programming and Optimization with Intel Xeon Phi Coprocessors

Here is a set of introductory videos from Colfax International on Parallel Programming and Optimization with Intel(R) Xeon Phi(TM) Coprocessors.

In this video episode we will introduce Intel Xeon Phi coprocessors based on the Intel Many Integrated Core, or MIC, architecture and will cover some of the specifics of hardware implementation.

视频 - 借助英特尔至强融核协处理器实现并行编程和优化

下面是 Colfax International 发布的一组关于借助英特尔(R) 至强融核(TM) 协处理器实现并行编程和优化的视频。

第 2.1 集 MIC 架构的用途
在本段视频中,我们将介绍基于英特尔集成众核(或 MIC)架构的英特尔至强融核协处理器,以及硬件实施的几点特性。

第 2.2 集 英特尔 MIC 架构详情
本视频将详细介绍英特尔 MIC 架构的一般属性,然后重点介绍矢量指令支持。

第 2.3 集- 英特尔架构对矢量指令的支持
在本段视频中,我们将介绍矢量指令,以及英特尔至强融核协处理器支持的指令。

Measuring Power on Intel® Xeon Phi™ Product Family Devices

Understanding power measurements and the issues associated with various power measurement methodologies is key to utilizing, procuring and deploying large HPC (High Performance Computing) clusters along with maximizing bottom line profit in the enterprise world. In the HPC space, large FLOPs/watt ratios are now a key design and procurement requirement as the operating costs of today’s petascale systems are on par with the acquisition costs of the actual supercomputer hardware itself (Subramaniam & Wu-chun, 2010).

  • Developers
  • Linux*
  • Server
  • Intel® Xeon Phi™ Coprocessors
  • HPC
  • FLOPS
  • KNL
  • Knights Landing
  • KNC
  • Intel® Many Integrated Core Architecture
  • Power Efficiency
  • Calculating “FLOP” using Intel® Software Development Emulator (Intel® SDE)

    Purpose

    Floating point operations (FLOP) rate is used widely by the High Performance Computing (HPC) community as a metric for analysis and/or benchmarking purposes. Many HPC nominations (e.g., Gordon Bell) require the FLOP rate be specified for their application submissions.

    The methodology described here DOES NOT rely on the Performance Monitoring Unit (PMU) events/counters. This is an alternative software methodology to evaluate FLOP using the Intel® SDE.

  • Developers
  • Professors
  • Students
  • Linux*
  • Server
  • Advanced
  • Intermediate
  • Intel® Software Development Emulator
  • FLOP
  • Knight’s Landing
  • Intel® SDE
  • HPC
  • Floating point operations
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Core™ processor family
  • Intel® Many Integrated Core Architecture
  • 使用英特尔® 软件开发仿真器(英特尔® SDE)计算 “FLOP”

    目的

    作为分析指标和/或基于性能指标评测目的,浮点运算 (FLOP) 速度广泛运用于高性能计算 (HPC) 社区。 许多 HPC 贡献者(比如戈登·贝尔)要求提交应用时注明 FLOP 速度。

    本文所述的方法不依赖于性能监控单元 (PMU) 事件/计数器。 它是一种使用英特尔® SDE 评估 FLOP 的替代性软件方法。

  • Developers
  • Professors
  • Students
  • Linux*
  • Server
  • Advanced
  • Intermediate
  • Intel® Software Development Emulator
  • FLOP
  • Knight’s Landing
  • Intel® SDE
  • HPC
  • Floating point operations
  • Intel® Xeon Phi™ Coprocessor
  • Intel® Core™ processor family
  • Intel® Many Integrated Core Architecture
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