Here is a list of recently published videos from Colfax International on Intel(R) Xeon Phi(TM) Coprocessors.
In this video we will discuss software tools needed and recommended for developing applications for Intel Xeon Phi coprocessors. We will begin with software that is necessary to boot coprocessors and to run pre-compiled executables on them.
Here is a set of introductory videos from Colfax International on Parallel Programming and Optimization with Intel(R) Xeon Phi(TM) Coprocessors.
In this video episode we will introduce Intel Xeon Phi coprocessors based on the Intel Many Integrated Core, or MIC, architecture and will cover some of the specifics of hardware implementation.
Understanding power measurements and the issues associated with various power measurement methodologies is key to utilizing, procuring and deploying large HPC (High Performance Computing) clusters along with maximizing bottom line profit in the enterprise world. In the HPC space, large FLOPs/watt ratios are now a key design and procurement requirement as the operating costs of today’s petascale systems are on par with the acquisition costs of the actual supercomputer hardware itself (Subramaniam & Wu-chun, 2010).
Floating point operations (FLOP) rate is used widely by the High Performance Computing (HPC) community as a metric for analysis and/or benchmarking purposes. Many HPC nominations (e.g., Gordon Bell) require the FLOP rate be specified for their application submissions.
The methodology described here DOES NOT rely on the Performance Monitoring Unit (PMU) events/counters. This is an alternative software methodology to evaluate FLOP using the Intel® SDE.
作为分析指标和/或基于性能指标评测目的，浮点运算 (FLOP) 速度广泛运用于高性能计算 (HPC) 社区。 许多 HPC 贡献者（比如戈登·贝尔）要求提交应用时注明 FLOP 速度。
本文所述的方法不依赖于性能监控单元 (PMU) 事件/计数器。 它是一种使用英特尔® SDE 评估 FLOP 的替代性软件方法。