I have a lecture I give to college classes on parallel programming In it, I carefully explain the reasons behind the transition to many core chips and then discuss the need for design patterns to help us do the right things. I then close with the critical role that OpenCL plays in the future of many core chips.
The task of constructing of identifying sequences for synchronous sequential circuits is one of the central problems in the design process. Genetic algorithm (GA) is one of the possible solutions of this task. It uses simulation of digital circuits to value the quality of potential solutions. Due this fact GA of input sequences generation are very slowly. In this paper we propose parallel versions of GA of this type that adapted for multi-core workstations. In our approach we organize several parallel threads.
Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In this paper we propose a new parallel fault simulation algorithm for multi-core workstations with common memory. We use dynamic fault grouping for each input test vector. Also each formed group is simulated in separate thread. Also we study the scalability of proposed algorithm. We report results for the ISCAS-89 benchmark circuits obtained on Intel’s MTL with 12 computational cores.
I thought that I would post this since one of my co-workers at Cadence will be gave a webinar on his experience parallelizing an existing application. The application and algorithms involved are really complex. It was especially interesting because it involves legacy code and also the development environment was Windows unlike many EDA applications which run on Linux/Unix. I really recommending watching.