Intel Xeon Phi Coprocessor

Resource Guide for People Investigating the Intel® Xeon Phi™ Coprocessor

This article identifies resources for anyone investigating the value to their organization of the Intel® Xeon Phi™ coprocessor, which is based on the Intel® Many Integrated Core (Intel® MIC) architecture. It is one of three such guides, each for people in one of the following specific roles:

  • Developers
  • Professors
  • Students
  • Linux*
  • Microsoft Windows* (XP, Vista, 7)
  • Microsoft Windows* 8.x
  • C/C++
  • Fortran
  • Advanced
  • server
  • Parallel Programming
  • Taylor Kidd
  • Intel Xeon Phi Coprocessor
  • MIC
  • Knights Corner
  • manycore
  • Many Core
  • KNC
  • Cluster Computing
  • Debugging
  • Development Tools
  • Intel® Many Integrated Core Architecture
  • Optimization
  • Parallel Computing
  • Porting
  • BKMs on the use of the SIMD directive

    We had an ask from one of the various “Birds of a Feather” meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences. The customer wanted to know BKMs (Best Known Methods) on the proper usage of the new OpenMP* 4.0 / Intel® Cilk™ Plus SIMD directive. I volunteered to create such a list. Investigating the topic more thoroughly, I discovered that there is already a vast amount of resources on vectorization and the use of the SIMD directive.

    Resource Guide for Intel® Xeon Phi™ Coprocessor Administrators

    This article makes recommendations for how an administrator can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This article is 1 of 3: For the Administrator, for the Developer, and for the Investigator. Someone who will administer and support a set of machines (individual/cluster) containing coprocessors. The assumption is that the following topics are of most interest to him. Administrative tools and configurations for the Intel Manycore Platform Software Stack (Intel MPSS) Technical support services Library support Language support Network infrastructure Installation documentation Cluster administration and FAQ Scripting support
  • Developers
  • Professors
  • Students
  • Linux*
  • Microsoft Windows* (XP, Vista, 7)
  • Microsoft Windows* 8.x
  • Server
  • C/C++
  • Fortran
  • Advanced
  • server
  • Parallel Programming
  • Taylor Kidd
  • Intel Xeon Phi Coprocessor
  • MIC
  • Knights Corner
  • manycore
  • Many Core
  • KNC
  • Cluster Computing
  • Debugging
  • Development Tools
  • Intel® Many Integrated Core Architecture
  • Parallel Computing
  • Porting
  • Resource Guide for Intel® Xeon Phi™ Coprocessor Developers

    This article makes recommendations for how a developer can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This is one of three articles: For the Administrator, for the Developer, and for the Investigator. Who is a Developer? Someone who will be programming on an Intel Many Integrated Core (Intel MIC) architecture. The assumption is that they are most interested in: Brief Introduction to the Intel MIC development environment Programming models Hardware architecture Software stack Coprocessor specific drivers and tools – Intel Manycore Platform Software Stack (Intel MPSS) Compilers Libraries Tools Examples and tutorials SW Developer’s Guide Programmer’s Guide Optimization Guide Getting help and other support
  • Developers
  • Professors
  • Students
  • Linux*
  • Server
  • C/C++
  • Fortran
  • Advanced
  • server
  • Parallel Programming
  • Taylor Kidd
  • Intel Xeon Phi Coprocessor
  • MIC
  • Knights Corner
  • manycore
  • Many Core
  • KNC
  • Cluster Computing
  • Intel® Many Integrated Core Architecture
  • Parallel Computing
  • Power Efficiency
  • The Chronicles of Phi - part 3 Hyper-Thread Phalanx – tiled_HT1 continued

    The prior part (2) of this blog provided a header and set of function that can be used to determine the logical core and logical Hyper-Thread number within the core. This determination is to be use in an optimization strategy called the Hyper-Thread Phalanx.

    The Chronicles of Phi - part 1 The Hyper-Thread Phalanx

    The term phalanx is derived from a military formation used by the ancient Greeks and Romans. The formation generally involved soldiers lining up shoulder to shoulder, shield to shield multiple rows deep. The formation would advance in unison becoming “an irresistible force.” I use the term Hyper-Thread Phalanx to refer to the Hyper-Thread siblings of a core being aligned shoulder-to-shoulder and advancing forward.

    Intel® Xeon Phi™ coprocessor Power Management Turbo Part 3: How can I design my program to make use of turbo?

    Previous blogs on power management and a host of other power management resources can be found in, “List of Useful Power and Power Management Articles, Blogs and References” at http://software.intel.com/en-us/articles/list-of-useful-power-and-power-management-articles-blogs-and-references. See [LIST] below in the reference section.

    SO WHEN IS TURBO USEFUL

    Let us cut to the chase and ask the two most important questions:

    Recettes de code pour le coprocesseur Intel® Xeon Phi™

    Cette page contient un recueil croissant de codes communément accessibles ou téléchargeables pouvant être exécutés sur les coprocesseurs Intel® Xeon Phi™.

    Si vous avez réalisé une promotion en amont d’un code communautaire, veuillez publier un thème de discussion sur le forum Intel® Many Integrated Core Architecture afin de nous le faire savoir, pour que nous puissions mettre la liste à jour.

    Dernières modifications :

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  • Intel Xeon Phi Coprocessor
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  • Советы по созданию программного кода для сопроцессора Intel® Xeon Phi™

    На этой странице содержится постоянно расширяемый, общедоступный или загружаемый код, который может выполняться на системах под управлением сопроцессоров Intel® Xeon Phi™.

    Если контрольный просмотр кода сообщества завершен, опубликуйте поток в форуме по архитектуре Intel® Many Integrated Core, чтобы мы смогли вовремя обновить этот список.

    Последние изменения:

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