Intel(R) Xeon Phi(tm) Coprocessor -- Cluster training - call for demand!

Intel is evaluating to offer a 4 hour web-based basic tutorial covering the fundamental principles of how to integrate an Intel Xeon Phi coprocessor into a Linux based cluster.

During the course each attendant would have remote access to a Linux server and be able to do each step as shown in the outline below.  The course will be given free of charge. Requirements are an Internet connection, a web browser, and Putty.   We are settling on the sharing technology we will be using, and will publish that at a later date.

Invitation to evaluate Intel® MKL Sparse Matrix Vector Multiply Format Prototype Package for Intel® Xeon Phi™ coprocessors

We are seeking interested parties to evaluate Intel® MKL SpMV Format Prototype Package for Intel® Xeon Phi™ coprocessors. Sparse Matrix Vector Multiply (SpMV) is an important operation in many scientific applications, and its performance can be a critical part of overall application performance. On Intel® Xeon Phi™ coprocessors, Intel® MKL 11.0 and later provide highly-tuned SpMV kernels for the compressed sparse row (CSR) sparse matrix storage format.

New Tools: Simple Performance Tools for the Intel® Xeon® processor line and the Intel® Xeon Phi™ coprocessor

Larry Meadows from Intel Corporation has developed two simple tools for the Intel® Xeon® processor line as well as the Intel® Xeon Phi™ coprocessor that allow a user to determine how well their application is using the machine.

Troubleshooting HOWTO: Bad hardware? MPSS? Configuration?

Are you having problems with your hardware (Cannot see your Intel(R) Xeon Phi(tm) coprocessor?  Sporadic accessibility?) or with the Intel(R) Manycore Platform Software Stack (Intel(R) MPSS) running reliably?

Attached to this post is a PDF "flowchart" that explains how you can troubleshoot the problem (note:  this applies if you are running the Linux* operating system on your host), and shows what information you will want to collect if you need to escalate your issue to your OEM provider or Intel.

What collateral/documentation do you want to see?

Do you have questions that you are not finding the answers for in our documentation?  Need more training, source code examples, on what specifically?   Help us understand what's missing so that we can make sure we develop documentation you care about (what is important, and what is nice to have)!   Thank you

FAQS: Compilers, Libraries, Performance, Profiling and Optimization.

In the period prior to the launch of Intel® Xeon Phi™ coprocessor, Intel collected questions from developers who had been involved in pilot testing. This document contains some of the most common questions asked. Additional information and Best-Known-Methods for the Intel Xeon Phi coprocessor can be found here.

The Intel® Compiler reference guides can be found at:

Few issues with mic and mpssd


As I described in another post, mpss-3.2.1 is running on kernel 3.13.10 perfectly (Fedora 20).

 I can run programs on the processor and have no problems except:

1. mpssd daemon  is taking 100% of one host cpu all the time.

2. If mpssd is not started the coprocessor fan is always on. When mpssd starts it goes off when there is no activity. Since people may not want to use the card all the time the default fan speed should be off or low it seems like.

GFlops on MIC

Hello Intel,

I wrote "a kind of" meta compiler to generate SIMD code on multi platform (x86, power, PHI, etc ...). I will present my work in the ISC 2014 in june. I am preparing the Super Computing conference, where I would like present to result on the Phi platform I have an issue.

I am trying to calculate the GFLOP/s of my application, a first approach will be to count the number of operations and divide by the elapsed time, as usually done for dgemm benchmark. Unfortunately I have thousands of lines ...

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