Intel® Many Integrated Core Architecture

Xeon Phi Power Management: Controlling C-states through Userspace

Hi

I have been trying to develop a runtime energy management library for Intel Xeon Phi using idle state control (C-states). I have read through a few blogs but I could not find answers to the following:

1. How can I implement control of C-states through userspace. Do I need to rebuild the MPSS service with userspace?

2. I have all power features enabled currently (cpufreq, corec6, pc3 and poc6). I can see the usage of the different idle states through

cat /sys/devices/system/cpu/cpu0/cpuidle/state*/usage (showing the usage of different cpuidle states??)

Using L1/L2 cache as a scratchpad memory

Dear all,

Explicitly cache control is a one of important feature in Xeonphi (MIC). How could I use the L1 or L2 as scratchpad memory and also sharing them data between the cores?

In addition,  is there any way to hack the MESI state of the cache line in the distributed tag directory (DTD)? 

Thanks in advance.

Regards

__MIC__ macro does not work

Hello everyone,

           To solve problems like this:   undefined reference to `_mm512_xxx_xxx(), I have added __MIC__ macro into my code.(https://software.intel.com/en-us/comment/1726413#comment-1726413)

          But, these code between the

#ifdef __MIC__   

xxxx

xxxx

#endif

         never won't be executed.   

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