Watercooler / Catchall

In-Target Probe?

I'm not sure which forum my question really belongs to. What I like to do is to essentially be able to acess the instruction addresses (as they are executed) and the data (and their addresses) as a program executes. After going wandering around a few intel sites, I noticed the "in-target" probe gives the capability to look at the data I'm interested in. However, I couldn't quite find any other details as to how I would be able to access that information. Can someone point me in the right direction?

- Thanks,
- Rao.

Accessing system temperature from .NET application

Hello,

We deploy one of our corporate applications on Intel PCs so i was hoping to integrate the functionality in Intel's Active Monitor into our application so that it can report back any problems with the fan or the CPU overheating.

Is there a way that I can programmatically access information about the system's temperature, fan speed, etc. in my .NET applications?

Any info would be much appreciated.

Regards,
Jason Mercer

#SS in #SS

I want to know how CPU behave when there's no stack available(SS:ESP points to an virtual address which is not mapped to physical memory). The environment is in protection-mode. Following is my understanding:

Because there's no PTE for stack, the instruction "push eax" will result in a #SS. Responding to this #SS, the CPU will push EFLAGS, CS, EIP and ERROR_CODE into stack and turn to exception handler. But the new push will generate new #SS for the same reason... and the process will deadlock here.

Is my understanding correct?

Thanks,
Min

Is opcode 0x82 valid?

I have two different versions of "IA-32 Intel Architecture Software Developer's Manual". In Table A-2 "One-byte Opcode Map", one says 0x82 is "Ev, Ib"(the same as 0x83)but the other says 0x82 is "Eb, Ib"(the same as 0x80). But in "instruction set reference", it seems 0x82 is never used(for example, instruction __add__). So, is 0x82 a valid opcode? If it is, how should I decode it?

Thanks

Message Edited by minwang on 10-21-2004 05:53 PM

how is physical memory "seen" by cpu?

Suppose I have 16M physical memory in my system. Is it true that cpu accesses all the physical memory by putting 0x000000-0xffffff on its address bus? If it is true, does it mean the minimal memory requirement for DOS is 1M(because 640k-1M area is mandatory for mapping for various purposes)? And how does the mapping work?Is it something like when system power up, it reads BIOS into physical memory area reserved for BIOS mapping?

Thanks,

Message Edited by minwang on 10-12-2004 01:03 AM

EOF for Shared Bus Architecture?

Last 2 years of Intel in single CPU space were not too bad. Hyperthreading, faster FSB, SSE3 etc.
But what about Dual and Quad CPU x86 systems ?
How long Intel will be sitting on shared bus architecture? It is really major problem, and no amount of cache on Xeon CPUs or FSB speedup is going to solve it. Hypertransport is flourishing meanwhile on multi-CPU IBM/Apple and AMD systems.
So, where is Intel going with shared bus/memory architecture? Will we be it the same place 2 years from now?
Cmon time to make some changes. Good CPUs need good memory bus.

About FPU/SSE determinism

I have a question about determinism in FPU and SSE computations. Suppose thatI have a mixed sequence ofboth FPUand SSE instructions. Then I run it on different types of Intel microprocessors keeping the same starting conditions (general registers, FPU registers, memory etc). Will the final results be bit-by-bit equalon all processors? Are there any rules to predict and avoid undetermined results of FPU or SSE computations?

Thank you.

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