Intel ISA Extensions

AVX-512 expectations

Announcement: http://software.intel.com/en-us/blogs/2013/avx-512-instructions

What isn't clear from this announcement is whether the future Xeon processor with AVX-512 support will actually be a socketed MIC, or a CPU (more precisely Skylake)? Is it coming to consumer CPUs in a similar timeframe? Developers might want to know, to determine whether to adopt AVX2+ or heterogeneous computing. The latter would benefit the competition more than it would benefit Intel.

Detailed idata.txt

Hello.
Does anyone know if there is a place where I can download or buy a detailed version of the "idata.txt" file that comes with pintools (extras\xed2-ia32\misc\) ?
Basically I need a complete list of all instructions (including AVX, AVX512, etc) in order to build my own assembler/disassembler.
The problem with the official PDFs is that it is not easy to extract the required information and sometimes it contains errors.
Thank you

 

SSE2 vectorized code seems to run slower than non-vectorized code

Hi everyone:

This is my first time posting to the forum. I have a lot of experience designing and optimizing assembly language routines for signal processing. Until recently, this was on what you might call predictable architectures (Moto 56k DSP and PowerPC). I am now doing this on an x86, and having difficulty understanding where timing changes are occurring.

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