Intel ISA Extensions

E8400 with Gigabyte G41M-ES2L Motherboard

I have an E8400 with Gigabyte G41M-ES2L Motherboard I have tried to load window xp (preferred OS)on it and I get a message that there is not enough memory and windows has stopped installation. I then tried to load Windows Vista Home Basic and it worked but then after only 2 - 5 days it would crash and come back up with Windows has encountered a serious error. Then after a day or 2 it would crash and not even come up in Safe Mode. I would then reload Vista and it would repeat the same process. What is wrong? I have downloaded all the Windows Updates.

[smp] Initialization

Hello,

I am working on implement the multiprocessor capability into MaRTE RTOS. I have read Intel Software Developer's Manual and other guides.

Currently I know that I have to send an INIT IPI and two STARTUP IPI that will be handled at 0x000VV000 where VV is a vector from the IPI message (from B.4.2 Using STARTUP IPI, Multiprocessor Specification v1.4) to wake up secondary processors (APs).

I would like to know how to allocate code in that address.

Problem with SSE2 code

Hi!

I have a problem with a SSE2 code, that I can`t resolve. The piece of code is this:

asm("movupd xmm1, [xp]");xp+=2;
asm("movupd xmm0 , [yp]");yp+=2;

asm("addpd xmm1, xmm0\n");

asm("movupd [yp], xmm1\n");

"yp" at this moment becomes null so I think this is "addpd"s fault because if "addpd" instruction is commented, yp keeps the reference.
Somebody knows about this? I`ve been with this for several hours and I can`t see it.

Thanks in advance!!! :)

AVX-ready 3D application just released

As part of the normal update ofa web-based 3D application,we have includedan AVX path intoday's official release, since after extensive validation it proved stable (well within SDE at least). The application is based on a pure software renderer and fall back to SSE if no AVX hardware/emulator is found.

You can try it here: http://www.zvisuel.com/planogrambuilder/

clflush over the LAPIC mapping

I am remapping the LAPIC registers page to some virtual address. During the remap procedure, virtual memory subsystem invalidates the TLB for the page and then does clflush over the region, looping from the page start to end with appropriate step.

Unfortunately, on the first clflush, for the lowest address, I get unexpected interrupt. The interrupt is syncronous, i.e. it happens with $eip pointing to clflush.

Is it allowed and correct to call clflush over the virtuall mapping of lapic ?

segmentation in 64bit

hello everyone,

I am quite new to intel low-level programming and I have a question regarding segmentation in 64bit.

Is it possible to use hardware segmentation in intel 64bit processors?

I have read in the intel developer manual(3A) that segmentation in 64bit is disabled but not completely. As I know the linux kernel uses segmentation for separating user and kernel space, therefore some functionalities are present. But is it possible to use hardware segmentation on a 64bit system inside a user process? As example in a linux user process?

Optimizing SSE2 code and beyond...

Given an flow of SSE2 instructions on Linux x86_64 Intel 5345 processor as below -

---------------(a)--------------
"movaps %xmm5, %xmm12 \n\t"
"mulsd %xmm15, %xmm12 \n\t"
"addsd %xmm2, %xmm12 \n\t"

"movaps %xmm9, %xmm0 \n\t"
"mulsd %xmm14, %xmm0 \n\t"
"addsd %xmm0, %xmm12 \n\t"

"movaps %xmm11, %xmm0 \n\t"
"mulsd %xmm13, %xmm0 \n\t"
"addsd %xmm0, %xmm12 \n\t"

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