Intel® Many Integrated Core Architecture (Intel MIC Architecture)

OFFLOAD_REPORT: Why is CPU Time smaller than MIC Time?

Hello,

from compiler-assisted offload code, I get the following offload report:

[Offload] [HOST]  [Tag 2] [CPU Time]        5.053540(seconds)
[Offload] [MIC 0] [Tag 2] [CPU->MIC Data]   1080 (bytes)
[Offload] [MIC 0] [Tag 2] [MIC Time]        6.122002(seconds)
[Offload] [MIC 0] [Tag 2] [MIC->CPU Data]   1032 (bytes)

However, I expected that the total CPU time on the host is always greater than the MIC time on the mic, since it includes the execution time on the mic according to:

Aligned Allocators with C++11 on the MIC?

Short version: is this possible?

Long version: I have tried to use aligned allocators either directly or indirectly for a couple of different projects using the Xeon Phi, and have yet to be successful in compiling it x0 My understanding is that the allocator rules / parameters / syntax changed (again) similar to this issue:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=51626

Which BLAS 2 operations in MKL are threaded on the Phi?

Hello,

I guess the subject line tells it all. I am specifically interested in the dgemv routine.The only reference I could find about this is the following web page:

https://software.intel.com/en-us/node/528540

where it is mentioned that the ?gemv routines are threaded with OpenMP* for Intel® Core™2 Duo and Intel® Core™ i7 processors. So, there is no threaded implementation of BLAS 2 for the Phi?

Best regards,

Ioannis E. Venetis

Ofload error - data transfer

Hello,

I am writing, because i have a problem with data transfer from a coprocessor to a host processor in offload mode. In brief: at the beginning of my computation, I transfer all data to a coprocessor (one array), After completion of calculation I want to transfer to a host processor only part of this array, but in result i get following error:

offload error: data transfer (base=0x75654640, size=7896016) not subset of existing allocation (base=0x75654640, size=4512008)

Here is example of source code:

OpenCL on Xeon Phi: no accelerators detected

 

Hi all,

I got stuck on making opencl work with Xeon Phi. Tried google, but not very useful. Maybe it is a trivial question, but I am very new to Xeon Phi. Please give me some hints. :)

I download a sample code from this tutorial https://software.intel.com/en-us/articles/using-the-intel-sdk-for-opencl-applications-xe-2013 and try to compile and run it. The compilation was fine. Problem is when I try to run it, I got an error

New to OpenMP on MIC: Master/Workers thread configuration

Hi all,

I'm new to OpenMP. I'm trying to implement a program that runs on a Xeon Phi card. The program consists of a master thread and worker threads. 
The workers maintain hash tables, one each, and the master sends commands to the workers to insert new elements, find elements and delete elements.
I've looked through some documentation but there's an abundance of constructs and I got a bit lost.
I thought I'd be able to do something like this:

Subscribe to Intel® Many Integrated Core Architecture (Intel MIC Architecture)