Terasic DE10-Nano Get Started Guide

Welcome to developing on FPGAs!

DE10-Nano Angle

The Terasic DE10-Nano development board, based on an Intel® SoC FPGA, provides a reconfigurable hardware design platform for makers, IoT developers and educators. Featuring two GPIO expansion headers, an Arduino* header, high-speed DDR3 memory, an HDMI* port and ethernet networking, the board provides a robust and feature rich platform to create many exciting IoT applications.

Developers and makers are invited to discover the performance of a low-power embedded processor integrated with the flexibility of programmable logic. Divided into two distinct parts, the Intel® Cyclone® FPGA SoC device is made of a hard processor system (HPS) and a Field Programmable Gate Array (FPGA). While the HPS is a general purpose processor (based on a dual-core ARM Cortex-A9* processor), the FPGA is a parallel processing engine on which you can create custom hardware to accelerate fixed function algorithms or for extending the I/O capabilities of the device.

Follow along with the chapters (pages) of this Get Started Guide to get your board up and running. We walk you through the assembly and set up, configuring the FPGA and then connecting your host PC to the board. Then we take you to the webpages hosted by board where you can play with the interactive web demos. After familiarizing yourself with the demos, head on over to the Projects page and check out some of the tutorials where you can learn more about the GPIO LED framework, details of the Fast Fourier Transform (FFT), and debugging applications with the ARM* DS-5 debugger. For more ambitious developers, head straight to the Program Your First FPGA Device or check out the On-board Accelerometer Tutorial (be careful when you shake the board!).

Whether you are an FPGA developer, software developer, maker, seasoned IoT developer, coding newbie, or just curious about FPGAs, we hope your experience with the Terasic DE10-Nano kit is both informative and fun.

Let's get started!

For more complete information about compiler optimizations, see our Optimization Notice.