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March 14, 2016
Richter, Dave said on Apr 24,2018
An extremely informative explanation about the code modernization. Do these parallelization, vectorization, and memory hierarchy mechanisms handle any data misalignment? Are their misalignment corrections or flags that indicate such. Could they be aligned automatically? One could think that data is inherent in memory management, but it is almost as if it is more of apart taken into CPU design consideration.
Would the topic of data alignment in relation to memory location play more of a role in the memory hierarchy or in the CPU design? The well-known CMP, SMP, and Hyper-threading designs deal with memory differently, and perhaps their virtual cores and how would they use any cache pipeline, but with the rapid growth of GPU technology within code modernization, how would an actual software design plan fit in? Imperative or declarative, sequential with excessive control-flow loops that cause performance hits, or would it take a tend towards more of a reactive layout? But what I am doing writing this? It must because I salute code modernization, but application software just might require more knowledge of this venture, and many words used during your description point to hardware and Microprocessor design as warranting more priority that the memory hierarchy.
Continued success to you in this research venture.
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