Intel® Developer Zone:
Virtualization

Intel® Virtualization Developer Community

Developers, take advantage of Intel® VT. Engage with our bloggers and on the Forum, and tell us what is important to you. Let us know what is successful for you, and what opportunities we should action to make this site and the tools within, more helpful to your endeavors.

  • Getting Started
    • Intelligent Queueing Technologies for Virtualization Newly added & still relevant
    • Virtualization Primer New
    • Glossary of Virtualization Technologies
    • Virtualization Usage Models
    • Creating a Virtual Machine on VMware* Tutorial
    • Why Software Vendors Need to Care about Virtualization
    • Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices

    • Some helpful acronyms

      ATA Application Targeted Accelerators
      BMC Baseboard management Controller
      Boxboro Platform for Nehalem EX (Intel® Xeon® processor 7500 series and Tukwilla
      DCM Data Center Manager
      EP Efficient Performance
      EPT Extended Page Tables
      ESI Enterprise Southbridge Interface
      EX Expandable Server
      FBD Fully Buffered DIMM
      GT/s Giga transfers per second
      HA Home Agent in QPI based systems
      ICH IO controller hub
      IMC Integrated Memory Controller
      IOH IO hub
      L1, L2 Respectively the first and second level caches
      LA Land Grid Array(a type of chip packaginig0
      LLC Last Level Cache (on each chip) or Longest Latency Cache
      MC Mission Critical or Multi-core
      MC Memory controller
      ME Manageability engine
      NM Node Manger
      NUMA Non-uniform Memory Access
      OEM Original Equipment Manufacturer
      PCI Peripheral Component Interface (specification)
      QPI Quick Path Interconnect (Pt to Pt links)
      RAS Reliability, Availability, Serviceability
      RMCP Remote Monitoring and Control Protocol
      SCTP Stream Control Transmission Protocol
      SDDC Single Device Data Correction
      SKU Stock Keeping Unit (i.e., product variant)
      SMB Scalable Memory Buffer
      SMB SMBus System Management Bus
      SMI Scalable Memory Interface
      SMT Threads Simultaneous Multi-threading Threads or HW cpus on each core (2 if enabled, 1 if not)
      SSExy xy generation of vector instructions 9sTreaming SIMD extensions)
      TDP Thermal Design Power
      TPM Trusted Platform Module
      TPV Third Party Vendor
      Turbo Technology enabling higher frequency execution for one or more cores
      TXT Trusted Execution Technology
      Tylersburg Platform for Nehalem EP (Intel® Xeon® processor 5500 series) and Westmere EP(Intel® Xeon® processor 5600 series)
Intel® System Studio 2014 Beta - Articles Archive
By Noah Clemons (Intel)Posted 02/19/20140
Overview What's New Overview Detailed New Feature Overview Intel® System Studio 2014 for Linux* - System Requirements Intel® System Studio - Perfect Fit for Wind River* Linux* (PDF) Build and Design for Performance Using Intel® Compiler in Eclipse* for Wind River* Linux* Devel...
Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview
By Sreelekshmy Syamalakumari (Intel)Posted 10/04/20133
Download Article Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview [PDF 780KB] Contents Executive Summary Introduction Intel Xeon processor E5-2600 V2 product family enhancements Intel® Secure Key (DRNG) Intel® OS Guard (SMEP) Intel® Advanced Vector Extensions (Intel® AVX): Floa...
Intel® System Studio 2014 for Linux* BETA - Release Notes
By robert-mueller-albrecht (Intel)Posted 09/28/20130
This page provides the current Release Notes for the Intel® System Studio 2014 BETA product. To get product updates, log in to the Intel® Software Development Products Registration Center. For questions or technical support, visit Intel® Software Products Support. Intel® System Studio 2014 BET...
Intel® System Studio 2014 for Linux* - Solutions, Tips and Tricks
By robert-mueller-albrecht (Intel)Posted 09/28/20130
Overview What's New Overview Detailed New Feature Overview Intel® System Studio 2014 for Linux* - System Requirements Intel® System Studio - Perfect Fit for Wind River* Linux* (PDF) Build and Design for Performance Using Intel® Compiler in Eclipse* for Wind River* Linux* Devel...
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APIC Virtualization Performance Testing and Iozone*
By Khang Nguyen (Intel)Posted 12/17/20130
  Introduction Virtual machine monitors (VMM) emulate most guest access to interrupts and the advanced programmable interrupt controller (APIC) in a virtual environment.  They also virtualize all guest interrupts. These activities require the exit and reentry of the virtual machines (VM), but t...
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The action of Accessed and Dirty bit for EPT
By Arthur L.1
Hi there, I write a piece of code to test the action of Accessed and Dirty bit of EPT in Intel(R) Core(TM) i3-4130 CPU @ 3.40GHz. Firstly I build a totally new EPT paging structure with A/D logging on, then run some operating system codes and log all the EPT violation (say trap log). At some point I paused the OS, parse the EPT paging structure and log all the entries built in the past period (say A/D log). Here I get some interesting points: Some EPT entries are built without either Accessed or Dirty bit set, does this mean that CPU only construct these entries but doesn't touch them? Some entries only exist in A/D log. Does A/D logging module has some bias or some mistake? These two logs (trap log and A/D log) should be the same according to my understanding, and when I tried in the previous CPU with A/D bit supporting, these two logs are exactly the same, though I cannot distinguish Accessed or Dirty in A/D log.   Thanks ahead, Arthur
[x86] Information request about the Global Descriptor Table (GDT) | Intel® Developer Zone
By Jean M.2
Hello, I am currently working on a forensics project (32 bits OS), and to reach one of my goals, I need to play a bit with the GDT. From what I understood, an instruction like call dword ptr [gs:0x10] does the following things : GS is used as a segment selector (16 bits) : The lower three bits indicate the privilege level of access and the descriptor table to be used. In my case, we'll consider we use the GDT. The higher 13 bits represent the entry index in the GDT. Let's call A the base address corresponding to GTD[GS>>3]. A is returned, and the processor computes A+0x10 and gathers the value at this address, called B. A simple call B instruction is the executed. This kind of instruction happends when the code wants to perform a syscall : this instruction allows calling the __kernel_vsyscall function without knowing its address. Correct me if I'm wrong, but I understood that : The base address A corresponds to a section of the userland memory called the Thread Control Block (...
[x86] Information request about the Global Descriptor Table (GDT)
By Jean M.1
Hello, I am currently working on a forensics project (32 bits OS), and to reach one of my goals, I need to play a bit with the GDT. From what I understood, an instruction like call dword ptr [gs:0x10] does the following things : GS is used as a segment selector (16 bits) : The lower three bits indicate the privilege level of access and the descriptor table to be used. In my case, we'll consider we use the GDT. The higher 13 bits represent the entry index in the GDT. Let's call A the base address corresponding to GTD[GS>>3]. A is returned, and the processor computes A+0x10 and gathers the value at this address, called B. A simple call B instruction is the executed. This kind of instruction happends when the code wants to perform a syscall : this instruction allows calling the __kernel_vsyscall function without knowing its address. Correct me if I'm wrong, but I understood that : The base address A corresponds to a section of the userland memory called the Thread Control Block (...
Task Switch and Page Fault
By water m.2
Hi, What should I do when  handle task switch, but the new TSS is not in current virtual address space? Shoud I inject a Page Fault Exception to the guest directly?
handl I/O instruction caused VM-Exit
By water m.2
Hi, I'm writting code to handl I/O instruction caused VM-Exit, exit reason is 30.My guest is Windows XP. After get information from Exit Qualification, I can handle insturctions when String instruction bit and REP prefixed bit is cleared. But If these two bits are set, the trouble appears. When I tried to read data from memory where guest ESI(or EDI) pointed, I want to translate the logical address into physical address contained in guest  ESI(or EDI). but during the tranlsation,  the Page Table is not presented. At this time, I tried to inject a Page Fault to WindowsXP by set VM-entry interruption-information to 0x80000B0E,  VM-entry instruction length to 0x0, VM-entry exception error code to many kinds of possible number. But failed. I'am not sure whether my solution is correct. Can any one give me some tips?
Issue when the kernel parameter intel_iommu=on is being used
By sridhar s.1
Hello, I am using DPDK 1.5 for development of host pmd for device “Connect X3”. I am observing issue  while the ConnectX3 device DMA to a memory which is allocated with rte_memzone_reserve_aligned() API . The issue(please refer ERROR below) has been observed if the system runs with the kernel parameter “intel_iommu=on”. ########## ERROR :##################################3 dmar: DRHD: handling fault status reg 302 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f883000 DMAR:[fault reason 01] Present bit in root entry is clear #################################### The reported "fault Addr" is the physical address which was returned by the Above API. I don’t see any issue with the same code when the system up with kernel parameter intel_iommu=off.   If I use kernel parameters intel_iommu=on and iommu=pt, then the following error has been observed. ####ERROR REPORT######## dmar: DRHD: handling fault status reg 2 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f...
registering vm_exit handler in VT-x
By ivan i.1
Hi all, I would like to ask how an VM_EXIT handler is registered in VMCS - could you give some example. As far as i know VM_EXIT handler is routine, it could  be defined as C function. My question is how to register that handler function and to trap VM_EXITs into that function. Could you give some API  or snippet.  I have one more question ... when the VM_EXIT  handler is register and the execution meets the VM_EXIT conditions what is the mechanism of invoking the VM_EXIT handler? Is the invoking of the registered VM_EXIT handler is performed by VT-x at hardware level or there is something more to be done? Best Regards
EPT cause triple fault
By Mingbo Z.4
Hi all, I am writing a simple runtime hypervisor, like hyperdbg, bluepill. At first it works fine. But when I enable EPT, the vm exits with triple fault (Exit reason 2). and the guest RIP was at the fist instruction in non-root mode after vmlaunch. There is no ept violation. I did some 1:1 direct mapping, since no ept violation, that would be no use at all. wired thing is, the same code will run on VMware virtual machine. My PC is Core i7, and I disabled multicore. and I use serial port with windbg.  I am confused, which instruction caused this triple fault? I change the first line of non-root mode to "mov edi, edi", still the same triple fault.    Best regards, Mingbo

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Reaching Technology From Blogs 7
01/14/20130

Ylian has written a blog about Intel AMT Setup and Configuration using TLS-PSK and TLS-PKI.    Ylian stumbled across an interesting issue while updating the provisioning functionality of the OpenDTK tool.  What Ylian found was that for developers who are building their own Intel AMT Activation software, they will be required to use a non-standard TLS stack (the .NET TLS stack does not work.)  Watch RTFB 7 and learn more about what Intel AMT developers must know about writing software to enable Intel AMT systems with TLS.


Down to Business 8
11/19/20120

Down to Business 7
11/19/20120

Down to Business 6
11/19/20120

Ylian Saint-Hilaire walks the audience through an introduction of Meshcentral.com.  Learn how to install the agent, how to add a “Mesh” and then how to remotely control your remote devices.  


Reaching Technology From Blogs Show 1
11/07/20120

In episode of RTFB (Reaching Technology From Blogs), Gael Hofemeier interviews Ylian Saint-Hilaire about two of his Meshcentral blogs: 


Intel® Virtualization Technology Pt. 1 of 3 -
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Intel® Virtualization Technology Pt. 1 of 3 - Virtualization Introduction [id:1127428458001]


Intel® Virtualization Technology Pt. 3 of 3 -
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Intel® Virtualization Technology Pt. 3 of 3 - Emerging Usage Models


Intel® Virtualization Technology Pt. 2 of 3 -
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Intel® Virtualization Technology Pt. 2 of 3 - Virtualization Usage Models


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Forum contributors

David Ott: a Senior Software Engineer with Intel's Software Solutions Group, David’s recent work focuses on various aspects of enterprise computing, including virtualization, energy efficiency, and security. David holds M.S. and Ph.D. degrees in Computer Science from the University of North Carolina at Chapel Hill.

Hussam Mousa is a Software Engineer with the System Optimization Technology Center (SOTC) at Intel. He works on virtualization performance analysis, focusing on I/O performance for enterprise class applications. He has several published papers on virtualization performance analysis in academic conferences. He received his PhD from the University of California Santa Barbara in 2010, and his Bachelors in Science from the American University in Cairo in 2002. He has been with Intel since 2007.

Karthik Narayanan is a software engineer at Intel working on enterprise and management applications, clustering, and high availability, on-demand computing, native and virtualized. His 4+ years at Intel were preceded with experience gained at software companies in NY and in India. Karthik earned his Bachelors in Engineering at Madras University, India; and his Master of Science in Computer Science at the University of Toledo.