Intel® Developer Zone:

Intel® Virtualization Developer Community

Developers, take advantage of Intel® VT. Engage with our bloggers and on the Forum, and tell us what is important to you. Let us know what is successful for you, and what opportunities we should action to make this site and the tools within, more helpful to your endeavors.

  • Getting Started
    • Intelligent Queueing Technologies for Virtualization Newly added & still relevant
    • Virtualization Primer New
    • Glossary of Virtualization Technologies
    • Virtualization Usage Models
    • Creating a Virtual Machine on VMware* Tutorial
    • Why Software Vendors Need to Care about Virtualization
    • Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices

    • Some helpful acronyms

      ATA Application Targeted Accelerators
      BMC Baseboard management Controller
      Boxboro Platform for Nehalem EX (Intel® Xeon® processor 7500 series and Tukwilla
      DCM Data Center Manager
      EP Efficient Performance
      EPT Extended Page Tables
      ESI Enterprise Southbridge Interface
      EX Expandable Server
      FBD Fully Buffered DIMM
      GT/s Giga transfers per second
      HA Home Agent in QPI based systems
      ICH IO controller hub
      IMC Integrated Memory Controller
      IOH IO hub
      L1, L2 Respectively the first and second level caches
      LA Land Grid Array(a type of chip packaginig0
      LLC Last Level Cache (on each chip) or Longest Latency Cache
      MC Mission Critical or Multi-core
      MC Memory controller
      ME Manageability engine
      NM Node Manger
      NUMA Non-uniform Memory Access
      OEM Original Equipment Manufacturer
      PCI Peripheral Component Interface (specification)
      QPI Quick Path Interconnect (Pt to Pt links)
      RAS Reliability, Availability, Serviceability
      RMCP Remote Monitoring and Control Protocol
      SCTP Stream Control Transmission Protocol
      SDDC Single Device Data Correction
      SKU Stock Keeping Unit (i.e., product variant)
      SMB Scalable Memory Buffer
      SMB SMBus System Management Bus
      SMI Scalable Memory Interface
      SMT Threads Simultaneous Multi-threading Threads or HW cpus on each core (2 if enabled, 1 if not)
      SSExy xy generation of vector instructions 9sTreaming SIMD extensions)
      TDP Thermal Design Power
      TPM Trusted Platform Module
      TPV Third Party Vendor
      Turbo Technology enabling higher frequency execution for one or more cores
      TXT Trusted Execution Technology
      Tylersburg Platform for Nehalem EP (Intel® Xeon® processor 5500 series) and Westmere EP(Intel® Xeon® processor 5600 series)
Intel® Xeon® Processor E7 v3 Product Family
By Khang Nguyen (Intel)Posted 04/15/20150
Based on Intel® Core™ microarchitecture (formerly codenamed Haswell) and manufactured on 22-nanometer process technology, these processors provide significant performance over the previous-generation Intel Xeon processor E7 v2 product family. This is the first Intel® Xeon® processor product fam...
Intel® System Studio 2014 - Articles Archive
By Noah Clemons (Intel)Posted 02/19/20140
Overview What's New Overview Detailed New Feature Overview Intel® System Studio 2014 for Linux* - System Requirements Intel® System Studio - Perfect Fit for Wind River* Linux* (PDF) Build and Design for Performance Using Intel® Compiler in Eclipse* for Wind River* Linux* Devel...
Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview
By Sreelekshmy Syamalakumari (Intel)Posted 10/04/20133
Download Article Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview [PDF 780KB] Contents Executive Summary Introduction Intel Xeon processor E5-2600 V2 product family enhancements Intel® Secure Key (DRNG) Intel® OS Guard (SMEP) Intel® Advanced Vector Extensions (Intel® AVX): Floa...
Intel® System Studio 2014 for Linux* BETA - Release Notes
By robert-mueller-albrecht (Intel)Posted 09/28/20130
This page provides the current Release Notes for the Intel® System Studio 2014 BETA product. To get product updates, log in to the Intel® Software Development Products Registration Center. For questions or technical support, visit Intel® Software Products Support. Intel® System Studio 2014 BET...
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Intel’s Cache Monitoring Technology Software-Visible Interfaces
By Khang Nguyen (Intel) Posted on 12/11/14 0
Introduction Intel‘s Cache Monitoring Technology (CMT) feature was introduced with the Intel® Xeon™ E5 2600 v3 line of server processors in 2014. Initial blog posts here ( and here (
Chromebooks and the new Citrix* Receiver for Chrome
By Colleen Culbertson (Intel) Posted on 09/10/14 0
For any of you still thinking of the Chromebook™ notebook computer as just a consumer browsing device, think again. It's no longer just notebook computers running the Chrome OS™ operating system, it's also Chromebox™ computing devices, ChromeBase,*  and more - indicating form factor is not a bloc...
Software Defined Storage with Intel® Enabling Technologies
By Thai Le (Intel) Posted on 06/27/14 0
Software-Defined Storage (SDS) is a software layer that manages storage infrastructure.  Software developers have the flexibility to use a variety of hardware, such as processors, network cards, and hard drives with their storage managing software to develop their own SDS solutions.  In this blog...
Intel® graphics virtualization update
By Sunil Jain, (Intel) Posted on 05/02/14 0
Traditional business models, built on graphics and visualization usages such as workstation remoting, VDI, DaaS, transcoding, media streaming, and on-line gaming, are beginning to draw open source attention, worldwide. Employees are becoming mobile. They want flexibility of working from any devic...
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Windows unable to detect vt-x even though enabled in BIOS with UEFI
By Amirul I.1
Hi! I have a question regarding to this problems, what did I found that mostly PC with UEFI bios having problems detecting the vt-x. My current PC is unable to detect the vt-x but my old pc detect the vt-x that using legacy boot. I have tried looking for the answers in blogs, facebook groups and asking people about this problem but got nothing for the solution. Here is details about my old and new PC: OLD PC ====== -Intel® Pentium® Processor E5700 - BIOS is America Megatrend with legacy boot only - OS Windows XP SP2 NEW PC ====== -Intel® Core™ i5-3230M Processor - BIOS is America Megatrend with secure boot - OS Windows 8.1 Pro Hopefully that Intel could do something to come out with solution for this kind of problem
Convertible EPT-violation #VE
By ja1232
According to a number of Intel press and documentation, it seems that the Haswell processors should have the new processor feature that allows certain EPT violations to be converted to #VE (Virtualization Exception) so that these violations can be made without VM exits. I have looked into a number of different Haswell processors, but none of them has this support, i.e. bit 18 of IA32_VMX_PROCBASED_CTLS2 MSR is 0. This feature is not supported on for example i7-4770, i7-4790, i7-4940. Is this convertible #VE feature available on commodity processors yet? If so, which processors? Thanks!
Correct LOCK CMPXCHG emulation when the destination operand is in separate pages
By Eugene K.1
How LOCK CMPXCHG instruction should be emulated if the destination operand crosses page boundary (and therefore can be in non-contiguous physical memory)? I see, KVM gives up emulation in this case:   static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt, unsigned long addr, const void *old, const void *new, unsigned int bytes, struct x86_exception *exception) { ... if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK)) goto emul_write; ... return X86EMUL_CONTINUE; emul_write: printk_once(KERN_WARNING "kvm: emulating exchange as write\n"); return emulator_write_emulated(ctxt, addr, new, bytes, exception); }   What is the approach for most correct emulation which is as close as possible to the native execution?  
How to enable virtualization in intel dual core processor E5400
By Jonathan A.1
How to enable virtualization in intel dual core processor E5400 Please help me in doing this Mother board is DG41RQ
vt-d posted interrupts support
By Rakesh B.1
Hello,         I have the S2600CP server board with cpu "Intel(R) Xeon(R) CPU E5-2620 v2 @ 2.10GHz" which supports for APICv, I had patched the linux kernel source 3.18.0 to support vt-d posted interrupts on direct assigned devices, Given in lkml "".         I had checked the vt-d specification document[1] that describes "Remapping hardware support for interrupt-posting capability is reported through the Posted Interrupt Support (PI) field in the Capability register (CAP_REG)", In which it returns as the posted interrupt is not supported.  The assigning the ixgbe network device is been done via VFIO assignment method.         [1]         Does the above hardware support vt-d posted interrupt for direct assigned device assignment or it requires any hardware to do this.   Thanks Rakesh
Intel VT-D and Intel X99 motherboards
By Ward H.1
Hi, I am thinking of buying a X99 motherboard that I can use for Vmware Workstation. The two brands that I am thinking of are ASUS and GigaByte. I have been looking into the Virtualization and plan on running VMWare Workstation 11.  So virtualize windows Server 2012, Windows 8.1 etc. Plus VMWare ESXi. So I think for the last one I need Vt-d. Now I have notice the the ASUS MB's have a few more options for VTD like: Vtd Azalea VCp optimizations. Interrupt Remapping Coherency Support (Non-ISoch) Coherency Support (ISoch) However the GigaByte board only allows me to turn VT-d on and off. So since I can't control these options would they be on by default on the GigaByte, is there anything 'Disadvantage' I have not being able to control them? (Or is all this a bit of a non-issue ?) BTW - I can understand people here might not know specifically about VMWare or the motherboards in question. For example I am wondering if say a board supports VT-d means that these options are inclu...
RSM and multiple cores
By MP1
Hi all, I am trying to understand a technology that makes use of SMM in relation to hypervisors (hypercheck), and I have a number of questions about SMM in general - I hope I am posting in the right forum. I'd be interested to understand the following: 1) I know that on SMI asserting, all cores (at different interruptible boundaries) will enter SMM: are there spurious cases where SMM is triggered on only less cores? 2) The RSM instruction is said to return the processor to the not-SMM state. Does it need to be executed on every processor in SMM mode? 3) If I am in SMM mode with all my cores (i.e. I wait until them all are in SMM with a mutex), if I execute RSM from one core, does it resume normal operations (i.e. the kernel code it was executing) while the others are left in SMM mode? I am asking because the Default Treatment of RSM (33.14.2) is not exactly clear to me in Intel's doc.   Thanks in advance.    
DCBX on XL710
By Chakravarthy N.1
Hi, I am trying to configure DCBX & ETS on Intel XL710 in Linux. Is it currently supported? dcbtool reports DCBX is not enabled and I could not find other any linux utility to configure ETS. Please let me know , if there is any config guide I can refer to to get it working. Thanks ~Chakri
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McAfee Next Generation Firewall on Oracle VM (OOW '14)

McAfee Next Generation Firewall on Oracle VM (OOW '14)

Reaching Technology From Blogs 7

Ylian has written a blog about Intel AMT Setup and Configuration using TLS-PSK and TLS-PKI.    Ylian stumbled across an interesting issue while updating the provisioning functionality of the OpenDTK tool.  What Ylian found was that for developers who are building their own Intel AMT Activation software, they will be required to use a non-standard TLS stack (the .NET TLS stack does not work.)  Watch RTFB 7 and learn more about what Intel AMT developers must know about writing software to enable Intel AMT systems with TLS.

Down to Business 8

Down to Business 7

Down to Business 6

Ylian Saint-Hilaire walks the audience through an introduction of  Learn how to install the agent, how to add a “Mesh” and then how to remotely control your remote devices.  

Reaching Technology From Blogs Show 1

In episode of RTFB (Reaching Technology From Blogs), Gael Hofemeier interviews Ylian Saint-Hilaire about two of his Meshcentral blogs: 

Intel® Virtualization Technology Pt. 1 of 3 - Virtualization Introduction

Intel® Virtualization Technology Pt. 1 of 3 - Virtualization Introduction [id:1127428458001]

Intel® Virtualization Technology Pt. 3 of 3 - Emerging Usage Models

Intel® Virtualization Technology Pt. 3 of 3 - Emerging Usage Models

Intel® Virtualization Technology Pt. 2 of 3 - Virtualization Usage Models

Intel® Virtualization Technology Pt. 2 of 3 - Virtualization Usage Models

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Forum contributors

David Ott: a Senior Software Engineer with Intel's Software Solutions Group, David’s recent work focuses on various aspects of enterprise computing, including virtualization, energy efficiency, and security. David holds M.S. and Ph.D. degrees in Computer Science from the University of North Carolina at Chapel Hill.

Hussam Mousa is a Software Engineer with the System Optimization Technology Center (SOTC) at Intel. He works on virtualization performance analysis, focusing on I/O performance for enterprise class applications. He has several published papers on virtualization performance analysis in academic conferences. He received his PhD from the University of California Santa Barbara in 2010, and his Bachelors in Science from the American University in Cairo in 2002. He has been with Intel since 2007.

Karthik Narayanan is a software engineer at Intel working on enterprise and management applications, clustering, and high availability, on-demand computing, native and virtualized. His 4+ years at Intel were preceded with experience gained at software companies in NY and in India. Karthik earned his Bachelors in Engineering at Madras University, India; and his Master of Science in Computer Science at the University of Toledo.