Intel® Developer Zone:

Intel® Virtualization Developer Community

Developers, take advantage of Intel® VT. Engage with our bloggers and on the Forum, and tell us what is important to you. Let us know what is successful for you, and what opportunities we should action to make this site and the tools within, more helpful to your endeavors.

  • Getting Started
    • Intelligent Queueing Technologies for Virtualization Newly added & still relevant
    • Virtualization Primer New
    • Glossary of Virtualization Technologies
    • Virtualization Usage Models
    • Creating a Virtual Machine on VMware* Tutorial
    • Why Software Vendors Need to Care about Virtualization
    • Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices

    • Some helpful acronyms

      ATA Application Targeted Accelerators
      BMC Baseboard management Controller
      Boxboro Platform for Nehalem EX (Intel® Xeon® processor 7500 series and Tukwilla
      DCM Data Center Manager
      EP Efficient Performance
      EPT Extended Page Tables
      ESI Enterprise Southbridge Interface
      EX Expandable Server
      FBD Fully Buffered DIMM
      GT/s Giga transfers per second
      HA Home Agent in QPI based systems
      ICH IO controller hub
      IMC Integrated Memory Controller
      IOH IO hub
      L1, L2 Respectively the first and second level caches
      LA Land Grid Array(a type of chip packaginig0
      LLC Last Level Cache (on each chip) or Longest Latency Cache
      MC Mission Critical or Multi-core
      MC Memory controller
      ME Manageability engine
      NM Node Manger
      NUMA Non-uniform Memory Access
      OEM Original Equipment Manufacturer
      PCI Peripheral Component Interface (specification)
      QPI Quick Path Interconnect (Pt to Pt links)
      RAS Reliability, Availability, Serviceability
      RMCP Remote Monitoring and Control Protocol
      SCTP Stream Control Transmission Protocol
      SDDC Single Device Data Correction
      SKU Stock Keeping Unit (i.e., product variant)
      SMB Scalable Memory Buffer
      SMB SMBus System Management Bus
      SMI Scalable Memory Interface
      SMT Threads Simultaneous Multi-threading Threads or HW cpus on each core (2 if enabled, 1 if not)
      SSExy xy generation of vector instructions 9sTreaming SIMD extensions)
      TDP Thermal Design Power
      TPM Trusted Platform Module
      TPV Third Party Vendor
      Turbo Technology enabling higher frequency execution for one or more cores
      TXT Trusted Execution Technology
      Tylersburg Platform for Nehalem EP (Intel® Xeon® processor 5500 series) and Westmere EP(Intel® Xeon® processor 5600 series)
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ept in multi core
By water m.1
hi, i have took a lot of time to solve the problem when enabled the ept. my purpose is , run different OS on different core. i can run Ubuntu 14.04 on the BSP now. then i start one AP. the AP run a simple real time OS which have just 3 tasks(with EPT enabled too), no any hardware access(no network card, no hard drive...), not enable mttr, not enable MMU. the new problem came out. when the AP runing, the Ubuntu on BSP hangs(only the mouse cursor can move, no any other resoponse), but the real time OS on AP seems OK. Both BSP and AP share the same VMM code. I want to know, what is the relationship between EPT and multi core? the memory type must be the same on every core?
How to set EPT's memory type
By water m.7
Hi, my guest is Ubuntu 14.04, and I test my code in VMware 10. When I launch vmx, the Ubuntu can run as VM correctly. But if  I enabled the EPT, the Ubuntu hangs. I have tried to set the memory type through mtrr, failed too. Is there any more detail information? Except the Xen link? May I make a suggestion? There are many questions in this forumn, and a lot of answer is reference the Xen or Manaual. I know these material is good, but could some one give a more detailed answer? I have read the Manaual serval times, and the Xen is complicate, it can not help sometime.
VT in Linux
By water m.1
Hi, i have been developing a sample program based on VT. Here is my case: Start Ubuntu 14.04 on PC. Start a char device driver in Ubuntu. The char device driver execute vmxon, initialize the vmcs, and execute vmlaunch.At this time, the Ubuntu is runing as a VM. My VMM is very simple ,just handle the CR VM-exit and CPUID VM-exit. When the char device driver finished, i can see the VMM is running, and Ubuntu also seems fine. But when i execute a command like "ls" in the terminal, nothing happend, the "ls" command did not give any reply.I have try to start a new application like firefox, there also no response too.   Now, i do not know how to solve this problem.
VMXON issue - OS X Mavericks
By roee l.1
I'm trying to run vmxon for a few days now and still no luck. Ive done the following: 1) check for VMX support using CPUID 2) allocate a VMX region in the kernel using :  IOBufferMemoryDescriptor::inTaskWithOptions(kernel_task, kIOMemoryPhysicallyContiguous , PAGE_SIZE)After the allocation, I zeroed all the bytes and copied the VMX rev id to the first 4 bytes of this region (Got the rev id using RDMSR on 0x480 and grabbing the 4 right bytes) - the value is 12 (hex) if that even matters. 3) Turned on cr4.vmxe,,,, cr4.pae. 4) Turned on A20 address line 5) Given : uint64_t physical address = region physical address. Run vmxon with &physical_address. What am I doing wrong?  thanks
LBR and Virtualization
By Yoav A.1
I'm using LBR to trace guest execution, each time before vm_enter I overwrite the MSR_LASTBRANCH_(N-1)_FROM_IP/TO values with a magic value (0xdeadbabe) and execute a few instructions and read out the values. sometimes a record is skipped in the LBR and contains the magic value. why would this ever happen? I've look at the errata for haswell and didn't see anything similar, and running a similar code on the host outputs a perfect sequential trace. could this be an hardware bug related to vmx? Regards Yoav
IOAT DMA / Crystal Beach 3 Specifications
By Reto A.4
Hi everyone, I am looking for specifications for the Crystal Beach DMA controller. So far I only found the register specifications in the Xeon Processor Data sheet. I've got a Ivy Bridge machine: Intel(R) Xeon(R) CPU E5-2670 v2 @ 2.50GHz running on an Intel Corporation C600/X79 series chipset. We want to build a DMA driver for our research operating system (non Linux/Windows/solaris/bsd based). So I am basically looking for a specification to the following device i.e. how to setup the descriptor chains etc. Intel Corporation Xeon E5 v2/Core i7 Crystal Beach DMA Channel 0 (rev 04)Thanks,  Reto  
Virtualization Environment Utilized the Intel(R) Enterprise Class SSD
By Thai Le (Intel)0
I recently published a blog on the benefits of Intel(R) Enterprise Class SSD that has the usage examples of the Intel(R) Enterprise Class SSD in the actual customer's environment. I figure that it might be useful for the developers in this forum to learn how other developers are using Intel hardware.  -Thai
The action of Accessed and Dirty bit for EPT
By Arthur L.1
Hi there, I write a piece of code to test the action of Accessed and Dirty bit of EPT in Intel(R) Core(TM) i3-4130 CPU @ 3.40GHz. Firstly I build a totally new EPT paging structure with A/D logging on, then run some operating system codes and log all the EPT violation (say trap log). At some point I paused the OS, parse the EPT paging structure and log all the entries built in the past period (say A/D log). Here I get some interesting points: Some EPT entries are built without either Accessed or Dirty bit set, does this mean that CPU only construct these entries but doesn't touch them? Some entries only exist in A/D log. Does A/D logging module has some bias or some mistake? These two logs (trap log and A/D log) should be the same according to my understanding, and when I tried in the previous CPU with A/D bit supporting, these two logs are exactly the same, though I cannot distinguish Accessed or Dirty in A/D log.   Thanks ahead, Arthur
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Forum contributors

David Ott: a Senior Software Engineer with Intel's Software Solutions Group, David’s recent work focuses on various aspects of enterprise computing, including virtualization, energy efficiency, and security. David holds M.S. and Ph.D. degrees in Computer Science from the University of North Carolina at Chapel Hill.

Hussam Mousa is a Software Engineer with the System Optimization Technology Center (SOTC) at Intel. He works on virtualization performance analysis, focusing on I/O performance for enterprise class applications. He has several published papers on virtualization performance analysis in academic conferences. He received his PhD from the University of California Santa Barbara in 2010, and his Bachelors in Science from the American University in Cairo in 2002. He has been with Intel since 2007.

Karthik Narayanan is a software engineer at Intel working on enterprise and management applications, clustering, and high availability, on-demand computing, native and virtualized. His 4+ years at Intel were preceded with experience gained at software companies in NY and in India. Karthik earned his Bachelors in Engineering at Madras University, India; and his Master of Science in Computer Science at the University of Toledo.