Intel® Developer Zone:

Intel® Virtualization Developer Community

Developers, take advantage of Intel® VT. Engage with our bloggers and on the Forum, and tell us what is important to you. Let us know what is successful for you, and what opportunities we should action to make this site and the tools within, more helpful to your endeavors.

  • Getting Started
    • Intelligent Queueing Technologies for Virtualization Newly added & still relevant
    • Virtualization Primer New
    • Glossary of Virtualization Technologies
    • Virtualization Usage Models
    • Creating a Virtual Machine on VMware* Tutorial
    • Why Software Vendors Need to Care about Virtualization
    • Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices

    • Some helpful acronyms

      ATA Application Targeted Accelerators
      BMC Baseboard management Controller
      Boxboro Platform for Nehalem EX (Intel® Xeon® processor 7500 series and Tukwilla
      DCM Data Center Manager
      EP Efficient Performance
      EPT Extended Page Tables
      ESI Enterprise Southbridge Interface
      EX Expandable Server
      FBD Fully Buffered DIMM
      GT/s Giga transfers per second
      HA Home Agent in QPI based systems
      ICH IO controller hub
      IMC Integrated Memory Controller
      IOH IO hub
      L1, L2 Respectively the first and second level caches
      LA Land Grid Array(a type of chip packaginig0
      LLC Last Level Cache (on each chip) or Longest Latency Cache
      MC Mission Critical or Multi-core
      MC Memory controller
      ME Manageability engine
      NM Node Manger
      NUMA Non-uniform Memory Access
      OEM Original Equipment Manufacturer
      PCI Peripheral Component Interface (specification)
      QPI Quick Path Interconnect (Pt to Pt links)
      RAS Reliability, Availability, Serviceability
      RMCP Remote Monitoring and Control Protocol
      SCTP Stream Control Transmission Protocol
      SDDC Single Device Data Correction
      SKU Stock Keeping Unit (i.e., product variant)
      SMB Scalable Memory Buffer
      SMB SMBus System Management Bus
      SMI Scalable Memory Interface
      SMT Threads Simultaneous Multi-threading Threads or HW cpus on each core (2 if enabled, 1 if not)
      SSExy xy generation of vector instructions 9sTreaming SIMD extensions)
      TDP Thermal Design Power
      TPM Trusted Platform Module
      TPV Third Party Vendor
      Turbo Technology enabling higher frequency execution for one or more cores
      TXT Trusted Execution Technology
      Tylersburg Platform for Nehalem EP (Intel® Xeon® processor 5500 series) and Westmere EP(Intel® Xeon® processor 5600 series)
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Task Switch and Page Fault
By water m.2
Hi, What should I do when  handle task switch, but the new TSS is not in current virtual address space? Shoud I inject a Page Fault Exception to the guest directly?
handl I/O instruction caused VM-Exit
By water m.2
Hi, I'm writting code to handl I/O instruction caused VM-Exit, exit reason is 30.My guest is Windows XP. After get information from Exit Qualification, I can handle insturctions when String instruction bit and REP prefixed bit is cleared. But If these two bits are set, the trouble appears. When I tried to read data from memory where guest ESI(or EDI) pointed, I want to translate the logical address into physical address contained in guest  ESI(or EDI). but during the tranlsation,  the Page Table is not presented. At this time, I tried to inject a Page Fault to WindowsXP by set VM-entry interruption-information to 0x80000B0E,  VM-entry instruction length to 0x0, VM-entry exception error code to many kinds of possible number. But failed. I'am not sure whether my solution is correct. Can any one give me some tips?
Issue when the kernel parameter intel_iommu=on is being used
By sridhar s.1
Hello, I am using DPDK 1.5 for development of host pmd for device “Connect X3”. I am observing issue  while the ConnectX3 device DMA to a memory which is allocated with rte_memzone_reserve_aligned() API . The issue(please refer ERROR below) has been observed if the system runs with the kernel parameter “intel_iommu=on”. ########## ERROR :##################################3 dmar: DRHD: handling fault status reg 302 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f883000 DMAR:[fault reason 01] Present bit in root entry is clear #################################### The reported "fault Addr" is the physical address which was returned by the Above API. I don’t see any issue with the same code when the system up with kernel parameter intel_iommu=off.   If I use kernel parameters intel_iommu=on and iommu=pt, then the following error has been observed. ####ERROR REPORT######## dmar: DRHD: handling fault status reg 2 dmar: DMAR:[DMA Write] Request device [01:00.0] fault addr 4f...
registering vm_exit handler in VT-x
By ivan i.1
Hi all, I would like to ask how an VM_EXIT handler is registered in VMCS - could you give some example. As far as i know VM_EXIT handler is routine, it could  be defined as C function. My question is how to register that handler function and to trap VM_EXITs into that function. Could you give some API  or snippet.  I have one more question ... when the VM_EXIT  handler is register and the execution meets the VM_EXIT conditions what is the mechanism of invoking the VM_EXIT handler? Is the invoking of the registered VM_EXIT handler is performed by VT-x at hardware level or there is something more to be done? Best Regards
EPT cause triple fault
By Mingbo Z.4
Hi all, I am writing a simple runtime hypervisor, like hyperdbg, bluepill. At first it works fine. But when I enable EPT, the vm exits with triple fault (Exit reason 2). and the guest RIP was at the fist instruction in non-root mode after vmlaunch. There is no ept violation. I did some 1:1 direct mapping, since no ept violation, that would be no use at all. wired thing is, the same code will run on VMware virtual machine. My PC is Core i7, and I disabled multicore. and I use serial port with windbg.  I am confused, which instruction caused this triple fault? I change the first line of non-root mode to "mov edi, edi", still the same triple fault.    Best regards, Mingbo
EPT Violation On a PTE free
By Saptarshi S.2
 Hi All,        Is it possible to configure EPT Entries or VMCS such that whenever a guest frees a page the host can instantaneously become aware of this. I have checked out the intel software developer manual 3B. But the closest I could  get is by causing a write violation in the EPT paging structure. But again, it did not seem proper as such writing violation can arise because of many other reasons as well. Besides, the whole performance of EPT would be destroyed if the guest does cache-writethrough.      I was testing this stuff with KVM and I could see that the host is not aware of  deallocations that  take place in the guest after allocations. Regards Saptarshi Sen        
Ambiguity with CR3-store/load exiting settings
By Eugene K.2
I have Intel(R) Core(TM) i5-2500 CPU. RDMSR on IA32_VMX_PROCBASED_CTLS MSR gives allowed-0 settings 0x0401E172, allowed-1 settings 0xFFF9FFFE. This means bits 15 (CR3-load exiting) and 16 (CR3-store exiting) of Primary Processor-Based VM-Execution Controls must be 1. However I can set them to zero and no any invalid VM entries happen. Why? CPU details: processor       : 0vendor_id       : GenuineIntelcpu family      : 6model           : 42model name      : Intel(R) Core(TM) i5-2500 CPU @ 3.30GHzstepping        : 7microcode       : 0x26cpu MHz         : 1600.000cache size      : 6144 KBphysical id     : 0siblings        : 4core id         : 0cpu cores       : 4apicid          : 0initial apicid  : 0fpu             : yesfpu_exception   : yescpuid level     : 13wp              : yesflags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl...
Intel VT-x and VT-d for app development
By Muhammad Khawar N.1
Hello, all! First some background on the situation:So, I'm going to be buying a new laptop soon, and one of my priorities is to do Windows Phone and Android app development on it. I don't play games, etc. so a high-end graphic chip is not my requirement. I need to run CPU-intensive simulation software like MATLAB occasionally so I need a good processor. Considering my budget and requirement and availability in my country; I've narrowed it down to two machines. An HP ProBook (which has an i7-3632QM processor + 8GB RAM), and an HP Pavilion (which has an i7-4702MQ + 4GB RAM). Now for the problem. Since I'll be doing app development, a good testing procedure is to test it on an emulator, for phone WP8 and Android... To run the emulators smoothly it is required that the processor support Intel Virtualization, and SLAT. Both processors do have Virtualization, but there is something called VT-d which is there for the Ivy Bridge but not the Haswell chip.  My questions are:1. Do I need VT-d ...
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Forum contributors

David Ott: a Senior Software Engineer with Intel's Software Solutions Group, David’s recent work focuses on various aspects of enterprise computing, including virtualization, energy efficiency, and security. David holds M.S. and Ph.D. degrees in Computer Science from the University of North Carolina at Chapel Hill.

Hussam Mousa is a Software Engineer with the System Optimization Technology Center (SOTC) at Intel. He works on virtualization performance analysis, focusing on I/O performance for enterprise class applications. He has several published papers on virtualization performance analysis in academic conferences. He received his PhD from the University of California Santa Barbara in 2010, and his Bachelors in Science from the American University in Cairo in 2002. He has been with Intel since 2007.

Karthik Narayanan is a software engineer at Intel working on enterprise and management applications, clustering, and high availability, on-demand computing, native and virtualized. His 4+ years at Intel were preceded with experience gained at software companies in NY and in India. Karthik earned his Bachelors in Engineering at Madras University, India; and his Master of Science in Computer Science at the University of Toledo.