Intel® Developer Zone:
Virtualization

Intel® Virtualization Developer Community

Developers, take advantage of Intel® VT. Engage with our bloggers and on the Forum, and tell us what is important to you. Let us know what is successful for you, and what opportunities we should action to make this site and the tools within, more helpful to your endeavors.

  • Getting Started
    • Intelligent Queueing Technologies for Virtualization Newly added & still relevant
    • Virtualization Primer New
    • Glossary of Virtualization Technologies
    • Virtualization Usage Models
    • Creating a Virtual Machine on VMware* Tutorial
    • Why Software Vendors Need to Care about Virtualization
    • Intel® Virtualization Technology for Directed I/O (VT-d): Enhancing Intel platforms for efficient virtualization of I/O devices

    • Some helpful acronyms

      ATA Application Targeted Accelerators
      BMC Baseboard management Controller
      Boxboro Platform for Nehalem EX (Intel® Xeon® processor 7500 series and Tukwilla
      DCM Data Center Manager
      EP Efficient Performance
      EPT Extended Page Tables
      ESI Enterprise Southbridge Interface
      EX Expandable Server
      FBD Fully Buffered DIMM
      GT/s Giga transfers per second
      HA Home Agent in QPI based systems
      ICH IO controller hub
      IMC Integrated Memory Controller
      IOH IO hub
      L1, L2 Respectively the first and second level caches
      LA Land Grid Array(a type of chip packaginig0
      LLC Last Level Cache (on each chip) or Longest Latency Cache
      MC Mission Critical or Multi-core
      MC Memory controller
      ME Manageability engine
      NM Node Manger
      NUMA Non-uniform Memory Access
      OEM Original Equipment Manufacturer
      PCI Peripheral Component Interface (specification)
      QPI Quick Path Interconnect (Pt to Pt links)
      RAS Reliability, Availability, Serviceability
      RMCP Remote Monitoring and Control Protocol
      SCTP Stream Control Transmission Protocol
      SDDC Single Device Data Correction
      SKU Stock Keeping Unit (i.e., product variant)
      SMB Scalable Memory Buffer
      SMB SMBus System Management Bus
      SMI Scalable Memory Interface
      SMT Threads Simultaneous Multi-threading Threads or HW cpus on each core (2 if enabled, 1 if not)
      SSExy xy generation of vector instructions 9sTreaming SIMD extensions)
      TDP Thermal Design Power
      TPM Trusted Platform Module
      TPV Third Party Vendor
      Turbo Technology enabling higher frequency execution for one or more cores
      TXT Trusted Execution Technology
      Tylersburg Platform for Nehalem EP (Intel® Xeon® processor 5500 series) and Westmere EP(Intel® Xeon® processor 5600 series)
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Which Intel processor supports the new virtualization controls?
By prism17293
I am looking for some information on what processor supports new virtualization features. Specifically, I am interested in the following features: The numbers in paranthesis denote the bit position in the secondary processor execution controls - 1. EPT-violation #VE (18) 2. VMCS shadowing (14) 3. Enable VM functions (13) 4. Virtual interrupt delivery (9) 5. Apic register virtualization (8) I have a sandybridge (cpuid leaf1 returns family 0x6, model 0xa, stepping id 0x7) and it does not support the above features. Does anyone know of a current/future cpu that supports these features? Any help is appreciated. Thank you.
Question on VMentry Checks
By prism17291
During vmlaunch/vmresume, several checks are performed on the guest state area.  I was wondering if anyone else had noticed that Guest RSP field is never checked for a non-canonical address. The virtualization spec talks about such checks for Guest RIP or GDTR or IDTR. I was wondering why this check was not done for the Guest RSP?
Handling VMExit reason 3 (INIT signal received)
By Yogi D.1
Hi.  I am writing a small OS-agnostic hypervisor as a teaching tool for my students.  The hypervisor code is loaded by the code I embed in a custom MBR on the boot device when the system boots.  The hypervisor code switches to 32-bit proected mode and then IA32e (64-bit mode).  It then sets up the hypevisor, EPT to protect the hypervisor from the guests, and launches a 16-bit "unrestricted" big real-mode (or unreal mode) guest.  All this is working perfectly.  The guest can make BIOS calls.  The hypervisor writes directly to the video buffer in order to provide debugging/status info.  The hypervisor is setup to VMexit minimally (e.g., I/O, APIC, MSRs, etc. are not monitored -- yet).  When the real-mode guest causes EPT violations, issues CPUID, etc. these cause VMExits as expected and the hypervisor handles them and resumes the guests. When the 16-bit guest issues an INIT IPI to itself using the APIC, I run into an infinite VMExit situation that my hypervisor cannot seem to recover ...
Forever Body Transformation Reviews Released by Tyler Tsujimoto and Candice Sadler
By Tyler T.0
There is additionally an e-book which food the entirety Forever Body Transformation review, and with the aim of indicates you will certainly recognize I beg your pardon? To expect and exactly how to stipulate your very own goals. Using their Forever Body Transformation Plan, they will expound recently I beg your pardon? Dishes is really Pro-FBT and specifically I beg your pardon? Foods are normally Anti-FBT and the instrument to sustain your metabolic value operating in ideal degrees. And additionally the wonderful feature pertaining toForever Body Transformation is the actuality with the aim of it comes having a 60 days 100 % money back ensure assure, so you possibly will test it away instead of a few kind of complete sixty days and additionally return this in issue it is not in point of fact instead of you personally. Forever Body Transformation is a emphasis loss list with the aim of might aid folks who are having problems of being round. That imply with the aim of every time a a...
How to identify processors with EPT accessed/dirty bits
By Tracy Camp1
I'm aware that software can check the IA32_VMX_EPT_VPID_CAP MSR to determine if the EPT table supports access and dirty bits...  However I would like to know how to identify a processor before I've purchased it that has this support. This is a common frustration I have with Intel parts - minor features vary quite a bit and don't seem to necissarily 'stick' in a linear progression of CPUID values due to various market differentiations.  Most of the time it doesn't matter too much, since most features are just an optimization for something that doesn't need to be implemented in software, however in this particular case, I'm not sure how to 'emulate' the lack of an accessed and dirty bit in the EPT tables of earlier EPT implementations in software.
Application or utility for testing virtualization on intel x540 T2
By Hitesh Prajapati1
Dear Sir/Madam, We have intel 10GbE Network Adapter X540-T2. Please guide me for the virtualization testing software for the adapter. I am new to this forum, also guide me that is this correct forum for the 10GbE network Adapter X540-T2. Reply me as early as possible. Thanks in advacne.  
Unexpected EPT Violations
By Ralf H.1
Hi, we're currently working in a project that involves extending the KVM hypervisor. While running the VM, we sometimes get EPT violations that shouldn't be possible from our understanding of the Intel documents. The scenario is as follow (we use Intel VT with EPT enabled):All guest paging structures (i.e., the paging structures _inside_ the VM) are set to non-writable on the last EPT level. In other words, whenever the guest OS writes to a guest paging structure (e.g. to map/free a page), this triggers an EPT violation. Now, "occasionally" the following happens:The VM performs a normal read operation somewhere in memory (doesn't seem to matter where). This then yields an EPT violation and bit 0,  bit 1, and bit 7 are set in the exit qualification field, bit 8 is cleared. According to the Intel specification (Table 27-7), this means that the EPT violation was caused by the MMU setting the dirty or accessed bit in the guest paging structures. At first, this makes sense since these ar...
Technological migration and virtualization, are they complementary?
By kcav@snet.net2
Rather than force a user to abruptly break away from routines that have become easy to perform, I think it might be a good idea to run Windows 7 in a virtual environment on the new platform; provided it is possible to hotkey from the new work environment to the old, and back to the new in a New York minute.   My interest in this came about when after changing from an old fashion notebook to an Ultraboook with a Touch screen I discovered the Start menu has changed, of course.  Also, I realized that using a slow browser on a fast platform doesn’t make sense, so I left behind my beloved IE8 with iGoogle homepage and changed to speedy Google Chrome.  Then I found myself wondering how to save Favorites, block pop-ups, establish and maintain trust relations, all things I had become somewhat familiar with doing, and now have to consciously think about again.  I am looking forward to making greater use of audio and video processing capabilities in the new 64-bit environment.  Since A/V file...
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Forum contributors

David Ott: a Senior Software Engineer with Intel's Software Solutions Group, David’s recent work focuses on various aspects of enterprise computing, including virtualization, energy efficiency, and security. David holds M.S. and Ph.D. degrees in Computer Science from the University of North Carolina at Chapel Hill.

Hussam Mousa is a Software Engineer with the System Optimization Technology Center (SOTC) at Intel. He works on virtualization performance analysis, focusing on I/O performance for enterprise class applications. He has several published papers on virtualization performance analysis in academic conferences. He received his PhD from the University of California Santa Barbara in 2010, and his Bachelors in Science from the American University in Cairo in 2002. He has been with Intel since 2007.

Karthik Narayanan is a software engineer at Intel working on enterprise and management applications, clustering, and high availability, on-demand computing, native and virtualized. His 4+ years at Intel were preceded with experience gained at software companies in NY and in India. Karthik earned his Bachelors in Engineering at Madras University, India; and his Master of Science in Computer Science at the University of Toledo.