CPU/FPGA Interaction View

Note

This is a PREVIEW FEATURE. A preview feature may or may not appear in a future production release. It is available for your use in the hopes that you will provide feedback on its usefulness and help determine its future. Data collected with a preview feature is not guaranteed to be backward compatible with future releases. Please send your feedback to parallel.studio.support@intel.com or to intelsystemstudio@intel.com.

Use the CPU/FPGA Interaction viewpoint to assess FPGA time spent executing kernels, overall time for memory transfers between the CPU and FPGA, and how well a workload is balanced between the CPU and FPGA.

To interpret the performance data provided in the CPU/FPGA Interaction viewpoint, you may follow the steps below:

  1. Define a Performance Baseline

  2. Assess FPGA Utilization

  3. Review Memory Transfers

  4. Determine Workload Impact

  5. Analyze Source

Define a Performance Baseline

Start with exploring the Summary window that provides general information on your application execution. Key areas for optimization include application execution time, tasks with high CPU or FPGA time, and FPGA OpenCL™ kernel execution time.

Use the Elapsed Time value as a baseline for comparison of versions before and after optimization.

Assess FPGA Utilization

Look at the FPGA Top Compute Tasks list on the Summary window for a list of OpenCL kernels running on the FPGA. Switch to the Bottom-up window and use the Computing Task Purpose / Source Computing Task (FPGA) grouping to view the hotspots for FPGA OpenCL kernels.

Tip

You can click a task from the FPGA Top Compute Tasks list to be taken to that task on the Bottom-up window.

Review the FPGA Utilization timeline, which shows how many OpenCL kernels and transfers are executing at the same time on the FPGA.

Review Memory Transfers

Look at the Data Transferred column on the Bottom-up window or the Computing Queue rows on the Platform window to view the FPGA OpenCL kernels and memory transfers.

Determine Workload Impact

The Context Switch Time metric on the Summary window shows the amount of time the CPU spent in context switches. Switch to the Platform window and hover over the timeline to view the reason for the context switch. In some cases, CPU context switches may represent CPU waits for the FPGA. Look at the FPGA Utilization line to identify times when the CPU may have been waiting on the FPGA and vice versa. For instance, when there is no FPGA activity, but CPU activity is high, it is likely that the FPGA is waiting for the CPU to complete a preparation step.

Analyze Source

Double-click the function you want to optimize to view its related source code file in the Source/Assembly window. You can open the code editor directly from the Intel® VTune™ Amplifier and edit your code (for example, minimizing the number of calls to the hotspot function).

For more complete information about compiler optimizations, see our Optimization Notice.
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