Intel® Xeon Phi™ Coprocessor

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Explicit Vector Programming in Fortran No longer does Moore’s Law result in higher frequencies and improved scalar application performance; instead, higher transistor counts lead to increased parallelism, both through more cores and through wider SIMD registers. To get the full performance benefit from these improvements in processor...
Autodesk University Shows How Intel Technology Powers 3D Design & Engineering Software At the Autodesk University event in Las Vegas, November 14-16, civil and commercial/industrial designers and manufacturers who use Autodesk software came together to see The Future of Making Things.
Exploit Nested Parallelism with OpenMP* Tasking Model The new generation, Intel® Xeon® processor Scalable family (formerly code-named Skylake-SP), Intel’s most scalable processor has up to 28 processor cores per socket with options to scale from 2 to 8 sockets. Intel® Xeon PhiTM processor provides massive parallelism with up to 72 cores per unit. More...
Recipe: Build NAMD on Intel® Xeon® and Intel® Xeon Phi™ Processors for Multi-node Runs This recipe describes a step-by-step process for getting, building, and running NAMD (scalable molecular dynamics code) on the Intel® Xeon Phi™ processor and Intel® Xeon® processor family to achieve better performance.
Recipe: Building NAMD on Intel® Xeon® and Intel® Xeon Phi™ Processors on a Single Node This recipe describes a step-by-step process for getting, building, and running NAMD (scalable molecular dynamics code) on the Intel® Xeon Phi™ processor and Intel® Xeon® processor E5 family to achieve better performance.
Michelle Chuaprasert
Students at the Intel® HPC Developer Conference Join Michelle Chuaprasert at “Meet the Experts” on Saturday 5:30-7:30 p.m. at the Intel® HPC Developer Conference. We’ll talk about our on-going support of the student developer community with conferences such as this as well as programs, learning and networking opportunities and more.
Track Reconstruction with Deep Learning at the CERN CMS Experiment This blog post is part of a series that describes my summer school project at CERN openlab. In the first post we introduced the problem of track reconstruction and the track seeds filtering. Today we are going to discuss the model architecture and the results.
Using Intel® MPI Library on Intel® Xeon Phi™ Product Family This document is designed to help users get started writing code and running MPI applications using the Intel® MPI Library on a development platform that includes the Intel® Xeon Phi™ processor.
CPUs are set to dominate high end visualization It is certainly provocative to say that CPUs will dominate any part of visualization - but I say it with confidence that the data supports why this is happening.  The primary drivers are (1) data sizes, (2) minimizing data movement, and (3) ability to change to O(n log n) algorithms.