Artículos de la Zona para desarrolladores Intel

11-feb.-2016
10:23 AM PST
Proof Points: Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family
Por Nguyen, Khang T (Intel)Publicado en 02/11/20160
This article provides a number of Memory Bandwidth Monitoring (MBM) example proof points and discussion fitting with the usage models described in previous articles.
11-feb.-2016
10:22 AM PST
Usage Models for Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family
Por Nguyen, Khang T (Intel)Publicado en 02/11/20160
Introduction Memory Bandwidth Monitoring (MBM), as introduced in the first article in this series, extends Cache Monitoring Technology (CMT) to provide per-thread memory bandwidth visibility. This article provides an overview of the key MBM usage cases, while subsequent blogs discuss proof poin...
11-feb.-2016
10:21 AM PST
Introduction to Memory Bandwidth Monitoring in the Intel® Xeon® Processor E5 v4 Family
Por Nguyen, Khang T (Intel)Publicado en 02/11/20160
Introduction Both cache and memory bandwidth can have a large impact on overall application performance in complex modern multithreaded and multitenant environments.  In the cloud datacenter for instance it is important to understand the resource requirements of an application in order to meet t...
11-feb.-2016
10:20 AM PST
Software Enabling for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family
Por Nguyen, Khang T (Intel)Publicado en 02/11/20160
This article provides a snapshot of some of the software-enabling collateral available for the Cache Allocation Technology (CAT) feature.
11-feb.-2016
10:17 AM PST
Usage Models for Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family
Por Nguyen, Khang T (Intel)Publicado en 02/11/20160
A number of usage models are possible given the flexible interfaces provided by the Cache Allocation Technology (CAT) feature, including prioritization of important applications and isolation of applications to reduce interference.
11-feb.-2016
10:14 AM PST
Introduction to Cache Allocation Technology in the Intel® Xeon® Processor E5 v4 Family
Por Nguyen, Khang T (Intel)Publicado en 02/11/20160
Introduction Intel’s Cache Allocation Technology (CAT) helps address shared resource concerns by providing software control of where data is allocated into the last-level cache (LLC), enabling isolation and prioritization of key applications. Originally introduced on a limited set of communicat...
03-feb.-2016
2:57 PM PST
What is OPNFV* and How Does Intel® ONP Align?
Por Michael Lynch (Intel)Publicado en 02/03/20160
Learn about Open Platform for Network Functions Virtualization* (OPNFV*), how it relates to Intel® Open Network Platform (Intel® ONP), and how Intel is contributing to OPNFV.
17-nov.-2015
9:54 AM PST
Using Open vSwitch* with DPDK for Inter-VM NFV Applications
Por Emani, Ashok (Intel)Publicado en 11/17/201516
This article walks you through configuration of OVS with DPDK for inter-VM application use cases. Create an OVS vSwitch bridge with two DPDK vhost-user ports, each connected to a separate VM, then use a simple iperf3 throughput test to evaluate performance.
10-nov.-2015
3:01 PM PST
Single-Root Input/Output Virtualization (SR-IOV) with Linux* Containers
Por Marco Righini (Intel)Publicado en 11/10/20152
This paper is a result of a joint CERN openlab-Intel research activity with the aim to investigate whether Linux Containers can be used together with SR-IOV in conjunction and complementary to the existing virtualization infrastructure in the CERN Data Centre. This solution could be potentially a...
01-nov.-2015
11:52 PM PST
Video Transcode Solutions: Simple, Fast, Efficient - Webinar
Por Brenda C. (Intel)Publicado en 11/01/20150
Video Transcode Solutions: Simple, Fast, Efficient - Online Webinar - Excel with Intel in delivering live and on-demand video faster, more efficiently, and at higher quality through the latest media acceleration technologies. Get the most performance from your media platform, and accelerate to 4K...
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